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Power supply requirements for the ATA LNAs
N.Wadefalk and S.Weinreb
September 18, 2003
The Low Noise Amplifier for the Allen Telescope Array is a three stage 0.5-11 GHz
MMIC (WBA13) based on 0.1*200 µm2 InP HEMT transistors from Northrop Grumman
Space Technology (NGST). This memo describes the power supply requirements for this
LNA. The amplifier has four connections for DC-power; two gates one drain and one
ground (Vg1, Vg2, Vd and gnd). The first section describes how to supply these voltages,
the second presents two possible biasing schemes and the third describes necessary overvoltage protection.
1.
Voltages, currents and their stability requirement
1.1
Vd
The optimum drain to source voltage for minimum noise of the transistors used in
WBA13 is approximately 0.5 V and quite temperature independent. However, Vd
supplied to the MMIC exhibits a large drop before it reaches the actual transistors. This
voltage drop is caused by on-chip resistors and is of course dependent on the current (Id),
which is a strong function of the physical temperature. At room temperature the
transistors seems to give lowest noise at about 85 mA/mm drain source current density,
while at 10 K this number drops to about 35 mA/mm. All three transistors in the MMIC
has a gate width of 200 µm which gives an optimum Id of 3*85*0.2≈50 mA and 20 mA
at 300 K and 10 K respectively. At the time this memo was written the WBA13 had not
yet been measured at 80 K and therefore the optimum Id at this temperature is unknown,
but is assumed to be 35 mA in the rest of this memo. Appendix 1 describes the LNA in
schematic form. The resistances responsible for the drop in Vd are 91, 66 and 48 ohm for
the three stages starting with the first. If the transistors are biased to sink the same
amount of current, the actual drain source voltage across the transistors will be higher for
the two last stages than the first. This is desirable since the transistors give lowest noise at
a low Vds but higher gain at a higher Vds. Our experience is that the optimum Vd for the
MMIC is 1.8 V at 300 K and 1.2 V at 10 K. Preliminary optimum Vd at 80K is 1.5 V. So
far we have tested about 40 WBA13’s from 3 different wafers from NGST’s cry 7 lot.
They all have the same optimum Vd both at 300 and 10 K, and therefore it should be safe
to say that the LNAs for the ATA can be biased at a fixed nonadjustable Vd.
Measurement of gain vs Vd at 80 K and a nominal Vd of 1.5 V is displayed in fig 1. This
measurement was made using a 50 ohm coaxial module with a WBA13 from Cry 7 4139049. The gain shows a +0.004 dB/mV dependence on Vd.
Fig 1.
1.2
Gain and Ids vs Vds at 89 K and 6 GHz.
Vg1 and Vg2
The optimum gate voltage is dependent on where the transconductance peaks on the gm
vs Vgs plot of the transistor. The gate voltage that gives maximum transconductance
varies significantly dependent on where on the wafer the transistor was situated. It also
varies from wafer to wafer. All 40 WBA13s assembled in modules so far used different
values for Vg. However, Vg1 was always equal to Vg2. This is an indication that the
transistors are almost identical if they are situated close to each other on the wafer. As
can seen from Appendix 1 there is an 11:1 voltage divider on the two gate lines. To be
sure that the LNAs can be biased properly Vg1 and Vg2 need to be adjustable from -3 to
+3 Volts. One reason why Vg1 would not be equal to Vg2 is if the transistors were very
leaky on the gates. The first gate is biased through a 50 kohm resistor, while the two last
transistors are biased through about 1 kohm. If the transistors have a very high Igs, the
voltage drop will be much higher in the first stage than the two last and Vg1 would have
to be made higher. With very few exceptions all the NGST wafers have very low gate
leakage at cryogenic temperatures. Measurements of gain vs Vg at 80 K and a nominal Id
of 35mA is displayed in fig 2. Vds was 1.5V and the two gate lines were tied together.
The gain shows a +0.0014 dB/mV dependence on Vg.
Fig 2.
1.3
Gain vs Vg at 89 K and 6 GHz
Id
Id is determined by both Vd and Vg. All 40 WBA13s assembled so far used the same Id;
50 mA at room temperature and 20 mA at 10 K. Noise has not yet been measured at 80 K
but it looks like Id will be about 30-40 mA. Measurements of gain vs Id at 80 K and a
nominal Vgs of 1.08 V is displayed in fig 3. Vd was 1.5 V and the two gate lines were
tied together. The gain shows a +0.07 dB/mA dependence on Id.
Fig 3.
2.
Gain vs Id at 89 K and 6 GHz
Different bias schemes
Two different bias schemes are commonly used to bias HEMT based LNAs; the constant
voltage and the constant current supply. In the constant current scheme Vd is kept
constant while Vg is continuously varied to give a constant Id. To be able to do this there
is a feedback loop in the power supply that measures Id and adjusts Vg to keep the current
constant. Vg might therefore be a function of time.
The constant voltage scheme supplies two constant voltages; Vg and Vd. If the I-V
characteristics of the HEMT vary over time, Id will also vary. The I-V characteristics are
strongly dependent on the ambient temperature and therefore the gain vs temperature for
the two different bias schemes has been measured. As can be seen from Fig 4 both bias
schemes exhibit about the same gain variation vs temperature at 80K. Constant voltage
shows an -0.012 dB/K gain slope, while constant current shows a -0.014 dB/K slope.
Since Vg1 and Vg2 control the same current, Id, they will have to be tied together in the
constant current scheme. This is not a problem as long as the gate current is low and the
three transistors on the MMIC are reasonable equal in I-V characteristics.
Fig 4.
Gain vs temperature for constant V and I schemes
This is the case for the Cry 7 wafer that will be used for ATA-3 in December and is also
likely to be the case for future wafers, but it can not be guaranteed. An advantage with
the constant current supply is that the two parameters that are set by the supply (Vd and
Id) are the same for all MMICs and therefore it can be built without potentiometers. Since
Vg is different for all MMICs the constant voltage supply will need to have an adjustable
gate voltage.
3.
Over-voltage protection
To be able to determine what kind of over-voltage protection is necessary, several
discreet 0.1*200 µm2 HEMTs from cryo 7 4139-049 were tested for breakdown voltage
both at 300 and 77 K temperature. SEM measurements of the gate length of this wafer
showed that the actual gate length is 79 nm. Breakdown at 300K occurred at Vds=2.7V
and Vgs=-0.5V and therefore the breakdown voltage is considered to be 3.2V drain-togate. Corresponding value for 77K was 3.1V. Of course, Vdg and Vds should be kept well
below the breakdown voltage at all times. Also, Vgs should be kept below +0.7V and
above -0.7V. These voltages are after the 11:1 divider on the gate, which means the
power supply should never output gate voltages outside the +/-7.7V range. The drain
voltage is recommended to be kept below 1.6 V and above -0.5 V at all times.
Because of the high failure rate of the 50 ohm coaxial modules for the prototype feeds,
also the Raytheon mHEMT MMICs were tested for breakdown. These MMICs are based
on 0.18 µm gate length GaAs transistors and the breakdown voltage turned out to be 5.7
V drain-to-gate. A possible reason for the failures of the 50 ohm LNAs is static charge
build-up on the feed arms. There’s a DC-block capacitor on the input that will protect for
this, but if the voltage becomes too high this capacitor can break down or the electrons
could decide to jump over the edge of it. To test for this, a capacitor was mounted on a
circuit board similar to the one used in the LNA and a voltage was applied over it. At 210
V no sign of breakdown was evident. Our power supply limited us to apply higher
voltages. The rated voltage of this capacitor is 50 VDC.
As can be seen from Appendix 1 the LNA module has diodes on both gate and drain for
over-voltage protection. Agilent’s GaAs Schottky HSCH series diodes were chosen for
this. They come in different configurations on flip-chips. On the gate there’s a single chip
containing two anti-parallel diodes. The drains use two chips; one with two diodes in
series for positive over-voltages and one with a single diode for negative. Fig 5 shows the
measured I-V characteristics of one of the chips with two anti-parallel diodes at different
temperatures. The diodes break at about Vf=1.5 V and If=250 mA. After breakdown they
always become a short circuit. Also Skyworks Solutions Inc has similar diodes at a much
cheaper price. They will be tested later.
Fig 5. I-V curve of HSCH-9551 at different temperatures
4.
Summary
For the three feeds due in December 2003 constant current and constant voltage schemes
seem equally good. The LNAs in these feeds will use MMICs from lot cry 7, wafer 4139049. This wafer has very low gate leakage at 80K and the three transistors on each MMIC
seem to be almost identical. This enables us to tie the two gates together which is a
necessity for the constant current supply. For ATA-32 we will have to rely on other
wafers which are not yet measured. It’s very likely that they will behave similarly to the
cry 7 wafers, but this can not be guaranteed. The safe way to go is the constant voltage
supply with two separate gate voltages. On the downside is that the gate voltages will
have to be set manually for each supply.
Preliminary bias is:
Vd=1.50V
Id=35.00mA
-3<Vg<3V (usually between 0 and 2V for Cry 7 4139-049)
Vd supplied to the LNA module must never fall outside the range, -0.5<Vd<1.6V.
Vg supplied to the LNA module must never fall outside the range, -7.7<Vg<7.7V.
Appendix 1
Vg1
10k
1k
Vg2
0.1uF
Vd
10k
0.1uF
1k
0.1uF
50
15
6.6
50k
50
15
10
6
6
76
IN
20
12
56
3T, 7um
spiral
5.2
1
50
28
1.5T, 7um
spiral
2
2T, 7um
spiral
3
5.2
0.9
200um
200um
1260
200um
28
0UT
150
6
6
1260
56
WBA13 MMIC
LNA module
Units are pF and ohms unless otherwise noted