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Name ______________________________
ES 330 Electronics II Homework # 5
(Fall 2016 – Due Monday, October 17, 2016)
Problem 1 (20 points)
Consider the NMOS transistor “current source” schematic circuit: [Note: This is more
appropriately called a “current sink.” Why?]
For VDD = 1.3 volts and using I REF = 100 A (microampreres), the design requirement
for the circuit cazlls for the output current IO to be nominally around 100 A. Transistors
Q1 and Q2 are geometry matched in layout and both have gate length L = 0.5 m and
gate width W = 5 m. The transistor parameters are as follows: the threshold voltage Vt
= 0.4 volt and k’n = 500 A/V2.
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(a) Find the value of resistor R that gives IO = 100 A.
(b) In addition, the Early voltage V’A of the NMOS transistors is V’A = 5 V/A. Find the
NMOS transistor’s output resistance ro.
Problem 2 (20 points)
You are presented with the current steering circuit shown schematically below:
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Find the value of current IO in terms of I REF and the device (W/L) ratios. For Q1 and Q2
denote the gate width-to-length ratios as (W/L)1 and (W/L)2 ; for Q3 and Q4 denote the
gate width-to-length ratios as (W/L)3 and (W/L)4.
Problem 3 (20 points)
Consider the basic “current mirror” in Figure 8.7 of Sedra & Smith.
(a) Suppose transistor Q2 has m times larger emitter area than that of transistor Q1.
[Note: This means that mI REF = IO, where m is the current transfer ratio.] Show that the
current transfer ratio (show the derivation of the equation) can be expressed as:
IO
m

I REF 1  m  1

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(b) If  is specified to be a minimum of 120, what is the largest current transfer ratio m if
the error between I REF and IO is less than or equal to 10% at most?
Problem 4 (20 points)
The two NMOS transistors in the “current mirror” below have equal channel lengths of L
= 0.5 m, W1 = 10 m, W2 = 50 m, nCox = 500 A/V2 and an Early voltage V’A = 10
V/m. The input bias current ID1 = 100 A. [Note: The gate-to-source voltage vgs, and
currents ii and io are all small-signal quantities.]
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Derive expressions for the input resistance Rin, the current transfer ratio Ais and output
resistance Ro.
Problem 5 (20 points)
Fiind the intriinsic gain of an NMOS transistor fabricated with a process for which k’n =
400 A/V2 and an Early voltage V’A = 10 V/m. The transistor process has a gate length
L = 0.5 m and is operated at VOV = 0. 2 volt. Suppose we require a transconductance
gm = 2 mA/V, what must (a) the drain current ID and (b) the gate width W be to meet this
requirement?
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What is the physical significance of the intrinsic gain of an active device?