Download List advantages and disadvantages of an np

yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project

Document related concepts

History of electric power transmission wikipedia , lookup

Tube sound wikipedia , lookup

Wireless power transfer wikipedia , lookup

Voltage optimisation wikipedia , lookup

Electric power system wikipedia , lookup

Islanding wikipedia , lookup

Mains electricity wikipedia , lookup

Opto-isolator wikipedia , lookup

Thermal runaway wikipedia , lookup

Electrification wikipedia , lookup

Power inverter wikipedia , lookup

Variable-frequency drive wikipedia , lookup

Alternating current wikipedia , lookup

Distribution management system wikipedia , lookup

Solar micro-inverter wikipedia , lookup

Power engineering wikipedia , lookup

Buck converter wikipedia , lookup

Power electronics wikipedia , lookup

Switched-mode power supply wikipedia , lookup

TRIAC wikipedia , lookup

Semiconductor device wikipedia , lookup

Transistor wikipedia , lookup

History of the transistor wikipedia , lookup

CMOS wikipedia , lookup

List advantages and disadvantages of an np-CMOS circuit.
What is Domino Logic?
Why is the clock feed through become problem and why is it occurring?
What is the charge sharing and why is it occurring?
Calculate the final output voltage of the two capacitors in parallel, 5pF and 2pF. The 5pF capacitor was
initially charged to 5V and the 2pF capacitor was initially charged to 0V.
List 3 advantages and 3 disadvantages of dynamic circuits.
Explain the difference between power and energy.
How is the energy used in a CMOS chip?
Describe the relationship between the transistor sizing and energy consumption.
List 3 ways to reduce dynamic power.
List 3 ways to reduce short-circuit power.
List 3 ways to reduce leakage power.
List 3 ways to reduce dynamic power without speed penalty.
Your CMPEN 411 class project chip has been fabricated and it draws 150mA of current from 5V power
supply, chip running at 150MHz. What is the power density?
You were given an inverter design to drive 0.1pF load with 0.1nsec delay. How would you arrange the
inverters on chip to drive 10pF load with 0.5nsec delay?
List 5 causes of delays in a CMOS gate.
List 5 ways to improve a CMOS gate speed.
Design the fastest 10 input AND gate in AMIS 0.5um CMOS technology. Show the transistor sizing of the
AND gate for fan-out of 2.
What is the turn-on resistances of PMOS and NMOS transistors in AMIS 0.5um CMOS technology
(transistor size L=0.6um and W =1.5um)?
Why is the MOS transistor considered as constant current device?
What is the Vth of the MOS transistor? What determines the Vth of the MOS transistor?
What is the minimum number of transistors needed to build an 8bit ripple carry adder in different logic
styles: static, dynamic, and pass transistor logic styles?
For static CMOS logic style, can we build 2 input AND gate with 2 NMOS transistors and 2 PMOS
transistors? Why or why not?