* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download C S U
Integrated circuit wikipedia , lookup
Power electronics wikipedia , lookup
Schmitt trigger wikipedia , lookup
Thermal runaway wikipedia , lookup
Surge protector wikipedia , lookup
Resistive opto-isolator wikipedia , lookup
Index of electronics articles wikipedia , lookup
Regenerative circuit wikipedia , lookup
Molecular scale electronics wikipedia , lookup
Opto-isolator wikipedia , lookup
Valve RF amplifier wikipedia , lookup
Rectiverter wikipedia , lookup
Wilson current mirror wikipedia , lookup
Electrical ballast wikipedia , lookup
Nanofluidic circuitry wikipedia , lookup
Negative-feedback amplifier wikipedia , lookup
Switched-mode power supply wikipedia , lookup
Operational amplifier wikipedia , lookup
Transistorβtransistor logic wikipedia , lookup
Current source wikipedia , lookup
Two-port network wikipedia , lookup
COLORADO STATE UNIVERSITY ECE 332: ELECTRONIC PRINCIPLES II HOMEWORK 2 1. Consider the classical biasing scheme shown in the figure below, using a 9-V supply. For the MOSFET, ππ‘ = 1π, π = 0, and π β² π = 2 ππ΄/π 2. W/L = 1. Arrange that the drain current is 1 ππ΄, with about one-third of the supply voltage across each of π π and π π . Use 22πΞ© for the larger one between π πΊ1 and π πΊ2 . What are the values of π π , π π , π πΊ1 , and π πΊ2 that you have chosen? Specify them to two significant digits. For your design, how far is the drain voltage from the edge of saturation? 2. Using the circuit topology shown in the figure below, arrange to bias the NMOS transistor at πΌπ· = 1 ππ΄ with ππ· midway between cutoff and the beginning of triode operation. (Hint: When the transistor is in cutoff region, the current flowing through the transistor should be zero. When the transistor enters the triode region from the saturation region, the beginning point is when Vgd=Vt.) The available supplies are ±5V. For the NMOS transistor, ππ‘ = 1π, π = 0, and π β² π = 2 ππ΄/π 2 . W/L = 1. Use a gate-bias resistor of 10πΞ©. Specify π π and π π· to two significant digits. Page 1 of 2 3. Using the feedback bias arrangement shown in the figure below with a 5-V supply with an NMOS device for which ππ‘ = 1π, and π β² π = 0.6 ππ΄/π 2 , W/L = 1. find π π· to establish a drain current of 0.2 mA. If resistor values are limited to those on the 5% resistor scale, what value would you choose? What values of current and ππ· result? 4. A variation feedback bias circuit from previous problem shown in the figure below using a 5-V supply with an NMOS device for which ππ‘ = 1π, π β² π = 6.25 ππ΄/π 2, W/L = 1, and π = 0, provide a design that biases the transistor at πΌπ· = 2 ππ΄, with ππ·π large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22πΞ© as the largest resistor in the feedback-bias network. What values of π π· , π πΊ1 , and π πΊ2 have you chosen? Specify all resistors to two significant digits. Page 2 of 2