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Standard cell layout Topics ! ! ! Layouts for logic networks. Channel routing. Simulation. ! ! ! Layout made of small cells: gates, flip-flops, etc. Cells are hand-designed. Assembly of cells is automatic: ! ! Slides courtesy Modern VLSI Design, 3rd Edition cells arranged in rows; wires routed between (and through) cells. Slides courtesy Modern VLSI Design, 3rd Edition Standard cell structure Standard cell design pin ! VDD Pitch: height of cell. Feedthrough area ! pullups n tub ! ! Intra-cell wiring pulldowns All cells have same pitch, may have different widths. VDD, VSS connections are designed to run through cells. A feedthrough area may allow wires to be routed over the cell. p tub VSS pin Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition Single-row layout design Routing channels ! cell cell cell cell cell Tracks form a grid for routing. ! ! Routing channel wire Horizontal track Vertical track height ! Different layers are (generally) used for horizontal and vertical wires. ! cell cell Slides courtesy Modern VLSI Design, 3rd Edition cell cell Spacing between tracks is center-to-center distance between wires. Track spacing depends on wire layer used. Horizontal and vertical can be routed relatively independently. cell Slides courtesy Modern VLSI Design, 3rd Edition Routing channel design ! ! ! Pin placement and routing Placement of cells determines placement of pins. Pin placement determines difficulty of routing problem. Density: lower bound on number of horizontal tracks needed to route the channel. ! a Density = 3 b c b c a Density = 2 c Maximum number of nets crossing from one end of channel to the other. a a before Slides courtesy Modern VLSI Design, 3rd Edition Two outputs: sum, carry. n1 bi ai X1 ! Generate candidates, evaluate area and speed. ! To generate a candidate: ! N1 X2 si ci n4 n2 bi ci b Layout methodology ai x1 bi c before Slides courtesy Modern VLSI Design, 3rd Edition Example: full adder layout ! b N4 N2 ! ! ci+1 ! Can improve candidate without starting from scratch. place gates in a row; draw wires between gates and primary inputs/outputs; measure channel density. ai x2 sum ci N3 n3 carry Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition A candidate layout Improvement strategies Density = 5 a ! Swap pairs of gates. ! Exchange larger groups of cells. ! b ! x1 x2 n1 n2 n3 n4 s ! Doesn’t help here. Swapping order of sum and carry groups doesn’t help either. This seems to be the placement that gives the lowest channel density. ! Cell sizes are fixed, so channel height determines area. cout c Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition Left-edge algorithm ! ! ! Example Basic channel routing algorithm. Assumes one horizontal segment per net. Sweep pins from left to right: ! A B C assign horizontal segment to lowest available track. A Slides courtesy Modern VLSI Design, 3rd Edition B C Slides courtesy Modern VLSI Design, 3rd Edition Limitations of left-edge algorithm ! B Some combinations of nets require more than one horizontal segment per net. A Vertical constraints ! Aligned pins form vertical constraints. ! Wire to lower pin must be on lower track; wire to upper pin must be above lower pin’s wire. B A B B A ? B A aligned Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition Dogleg wire ! Rat’s nest plot A dogleg wire has more than one horizontal segment. A B B A Slides courtesy Modern VLSI Design, 3rd Edition ! Can be used to judge placement before final routing. Slides courtesy Modern VLSI Design, 3rd Edition Simulation ! Types of simulation Goals of simulation: ! ! ! ! functional verification; timing; power consumption; testability. ! Circuit simulation: ! Timing simulation: ! ! ! Gate simulation: ! Models for gate simulation: ! ! ! Example: switch simulation + ! ! 0 c + logic gates as primitive elements. d X 1 0X zero delay; unit delay; variable delay. 1 0 c models fault propagation (more later). Slides courtesy Modern VLSI Design, 3rd Edition Slides courtesy Modern VLSI Design, 3rd Edition Example, cont’d. + 0 c + o b a Fault simulation: ! transistors as semi-ideal switches. Slides courtesy Modern VLSI Design, 3rd Edition Types of simulation, cont’d. ! simple analog models to provide timing but not detailed waveforms. Switch simulation: ! Slides courtesy Modern VLSI Design, 3rd Edition analog voltages and currents. d 10 10 o b a 10 0 c Slides courtesy Modern VLSI Design, 3rd Edition 10 X1