Download Level-Shifting MOSFET Driver

Theory of Operation
Circuit: Level-Shifting MOSFET Driver
Written: Dan Corriero, Bryce Salmi
Figure 1: The level-shifting MOSFET drive schematic shown with test circuitry.
MOSFET Driver Overview
The UC2524 Pulse-Width Modulator (PWM) integrated circuit generates a PWM signal
used to control the DC/DC buck converter switch. Figure 1 shows the level-shifting MOSFET
driver implemented with test circuitry as indicated by the dashed boxes. The PWM signal is
generated by using the wire-ORed open-collector pins to pull down the solar panel voltage
through a pull-down resistor. Both transistors in the UC2524 are represented by the single Q1 in
a wire-ORed configuration.
Due to NASA derating, p-channel MOSFET Q4 must have a gate-to-source voltage
(Vgs) of 30V or more. Devices which were appropriate for use in the Maximum Power Point
Tracker (MPPT) DC/DC buck converter had a Vgs of 20V which failed this requirement. The
source of Q4 is connected to the solar panel and the gate was subject to the 0V ground when
driven into the on state with a normal MOSFET driver. Due to this, a level-shifting MOSFET
driver was required to reduce the voltage difference experienced between the gate and source.
The gate of Q4 is experiences a maximum Vgs of half the solar panel voltage. The lowest solar
panel voltage expected during proper operation is about 15V, resulting in a Vgs of 7.5V, which is
large enough to fully turn on Q4. Assuming ideal components, a maximum solar panel voltage of
about 22.2V is also expected, resulting in a Vgs of 11.1V, meeting NASA derating requirements.
MOSFET Driver Operation
Referring to Figure 1, the operation of the level-shifting MOSFET driver will be
analyzed. The UC2524 output wire-ORed BJTs (Q1) are operated at an ideal 300 kHz switching
frequency. Q1 is placed into cutoff and saturation at the switching frequency to produce the
PWM signal. A resistive divider implemented with R1 and R2 are used to complete the circuit
and conduct current through Q1 to ground. Since R1 and R2 are the same value, exactly half the
solar panel voltage simulated with V2 is presented to the output of the voltage divider. At
maximum panel voltage, the PWM signal applied to the BJT totem pole will switch between
22.2V and 11.1V. Since the output of the UC2524 pulls VCC down when in the on state, the
resistive divider inverts the PWM signal. Operation with maximum panel voltage and a diode
voltage-drop of 600mV is assumed for the remainder of this document.
The BJT totem pole represented by transistors Q2 and Q3, NPN and PNP respectively, is
used to efficiently apply a high current into and out of the gate of MOSFET Q4. Assuming the
system starts with Q1 in the on state and the gate of Q4 charged to the solar panel voltage minus
a diode voltage-drop (about 21.6V), Q2 is in cutoff because the NPN device base voltage is
11.1V, lower than the emitter voltage, and Q3 is saturated because the PNP device base voltage is
lower than its emitter voltage, which is connected to the gate of Q4. The charge on the gate of Q4
drains to ground through R4 (0Ω) until the voltage on the gate decreases to equal 11.1V plus a
diode drop (about 11.7V). At this point, Q3 becomes reverse-biased since the base voltage is
within a diode voltage-drop of the emitter. When Q1 switches into the off state, 22.2V is applied
to the base of Q3 which further drives the PNP device into cutoff. Q2 is driven into saturation
since the gate is still at 11.7V. Current flows from the solar panel into the gate, through R4, until
the gate voltage has risen to 21.6V. When the gate has fully charged, Q2 reverse-biases since the
base and emitter voltages are within a diode voltage-drop of each other. This process repeats
itself for every switching cycle and performs the level-shifting function required to meet NASA
derating requirements.
Q2 and Q3 are nearly equivalent to shorted wires when they are fully on, allowing high
currents to flow through them, into and out of the gate of Q4. MOSFET gates have an associated
charge to them due to capacitance and cannot instantly change voltage. Therefore, the larger the
current the that flows into the gate to charge the capacitance, the faster the MOSFET turns on.
The totem pole driver implemented with Q2 and Q3 allows high currents to develop and is
appropriate for fast switching. Additionally, the totem pole driver is non-inverting, which means
that the inverted PWM signal from R1 and R2 is applied to the gate of Q4. Since Q4 is a pchannel device, another inversion to the PWM signal occurs, changing the signal into the
intended non-inverted PWM signal that is then applied to D1 and L1 of the buck converter.
Capacitor C6, resistor R4, and diode D3 are placed in the drive circuit to allow for speedup of the switching waveform and ringing suppression. If overshoot and/or ringing was noticed
on the gate, a small resistance could be placed at R4 to suppress these effects. Series resistance
between the MOSFET driver and Q4 reduces charging current and slows the switching rise and
fall times. C6 is a “speed-up” capacitor, which reduces the rise time when R4 is increased from
0Ω. The switching waveform can be viewed as a square wave with high frequency harmonics on
its edges. C6 appears as a short circuit to high frequencies, resulting in a slightly faster rise time.
D3 is used to discharge the gate quickly when R4 is larger than 0Ω. Depending on the value of
R4, the voltage drop across the forward-biased diode is smaller than that across R4, providing a
path of least resistance for high currents from the gate into ground, and reducing the fall-time.