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LAB ASSIGNMENT- DESIGN AND SIMULATION OF CIRCUITS USING MULTISIM
DESIGN 1
1. Signal limit detector
The circuit is designed to detect when the input voltage goes outside the range of +2.5V and +
3.5V.When the input voltage goes beyond these two limits an LED lights up and it stays on. The circuit
should incorporate a manual reset to switch the LED off.
The available components are comparator 339, a single quad NOR gate, resistors and 5V power supply.
Since there are two reference voltages there should be two comparator circuits.
The comparator circuit has two resistors, R1 and R2. For the resistor R1 I choose the value to be equal to
1KΩ. The supply voltage for both comparators is equal to 5V. The values of R2 for both comparator
circuits are calculated as follows
For comparator with 2.5V reference voltage
2.5=( R2/R1+R2)*5
But R1 =1KΩ
2.5= (R2/1+R2)*5
2.5(1+R2)=5R2
2.5+2.5R2=5R2
R2=1KΩ
For comparator with 3.5 V reference voltage
3.5=5*R1/(R1+R2)
But R1=1KΩ
3.5(1+R2)=5R2
3.5+3.5R2=5R2
3.5=1.5R2
R2= 3.5/1.5
=2.333KΩ
The manual reset will include a latch (flip-flop), and for the flip-flop I choose to use j-k flip-flop.
The circuit is constructed as follows.
2. MOSFET SWITCHING
Operation of a MOSFET
A MOSFET in full means "metal oxide semiconductor device". The main features of a MOSFET
include the following: Mosfet is a voltage controlled FET. If differs from JFET in that it has a gate
that is electrically insulated from the n-channel or the p-channel by an insulator mostly silicon
dioxide or glass.
The MOSFET is shown in the figure below:
Q1
2N7000
The MOSFET consist of four terminals namely: the gate, source, drain and the substrate. The
MOSFET can be N-channel or P-channel
P-Channel MOSFET
A P-channel mosfet consist of a p-channel region between the source and the gate.
Design
Design a transistor with the following specifications:
Vcc (v)-10
Ic (mA)-4
AV(dB)-14
Frequency Low hertz- 100
Frequency of 100Hz will affect the choice of the coupling capacitor.
Design procedure
Allow VCE=0.5VCC. The voltage VCC=10V therefore VCE=5V
The design of the collector and emitter resistors
Since the emitter current is nearly equal to the collector current we have
IC(RC+RE)=VCC-VCE
4*10^-3(RC+RE)=5
RC+RE=1.25KΩ
Assuming hfe min=100, and we are given Av= 14dB, we can calculate the ratio of the output to input
voltage.
20log(Vo/Vi)=14
log(Vo/Vi)=0.7
Vo/Vi=10^0.7
=5.0118
I take the voltage gain Av to be equal to 5.
Therefore RC/RE=5 which implies that RC=5RE
6RE=1.25KΩ
RE=208Ω taking RE to be taking RE to be 210Ω the value of RC is given by 210*5=1050 Ω
The voltage across the emitter side VE is given by VE=ICRE
=4*10^-3*210
= 0.84V
The base voltage assuming silicon transistor is given by 0.84V+0.7V= 1.54V
The maximum base current is given by IC/hfe min= 4 mA/100= 4uA.
Now let the current in R1 and R2 (IDIV) be about 5 to 10 times IB, so IDIV
= VCC / (R1 + R2) = say 10 IB (max) and since IB can now be neglected relative to IDIV,
VB = R2 / (R1 + R2) × VCC
10/(R1+R2)=10*4*10^-3
R2*10/(R1+R2)=0.84V
10R2=0.84R1+.084R2
9.16R2=0.84R1
R1=10.9R2
R1=11R2
10/12R2=4*10^-2
10=4*10^-2*12*R2
10=0.48R2
R2=20.8333
R1=11R2
=11*20.83
=229Ω
3) Voltage controlled oscillator