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Design and Simulation of Discrete-Time Cellular Neural Network by
Negative Differential Resistance Devices
Yaw-Hwang Chen, Long-Xian Su, Kwang-Jow Gan, Cher-Shiung Tsai, Dong-Shong Liang, Chi-Pin
Chen, 溫俊明 and 塗俊達
Department of Electronic Engineering, Kun Shan University of Technology
(NSC93-2215-E-168-002)
i) 2-, 3-, or n-dimensional array of
Abstract
Resonant tunneling diodes(RTD’s) have found
ii) mainly identical dynamical systems,
various application in high-speed digital and
called cells, which satisfies two properties:
analog circuits due to their specific advantages
associated with the unique folded-back
negative differential resistance (NDR) I-V
iii) most interactions are local with a finite
radius r ,and
iv) all state variables are continuous valued
characteristics.
In this paper we realized negative differential
resistance (NDR) I-V curve of RTD by
negative differential resistance devices. The
NDR device is composed of metal-oxide
semiconductor field-effect transistor (MOS)
devices. The discrete-time cellular neural
signals.
A typical example of a cell C (i , j ) of a
network cell is composed of NDR devices.
Therefore, the DT-CNN can be fabricated by
standard CMOS process.
are defined input, state, and output voltage
respectively.
I.
Introduction
The cellular neural networks were invented by
Chua and Yang in 1988. It is in order to solve
real-world problems in image processing,
robotics, motion video and many other
complex computational problems. Therefore
evokes the widespread discussion and there
have been documented in the first two
IEEE International Workshops on Cellular
Neural Networks and their Application in
1992, while retained the two basic concepts of
local connectedness and analog circuit
dynamics.
Definition: The CNN is a
cellular neural networks is shown in figure 1,
where the suffices u, x, and y denote the
input, state, and output respectively.
Therefore node voltage Vuij , V xij and V yij
C is a linear capacitor; R x and R y are
linear resistors; I is an independent current
source; I xu (i, j; k , l ) and I xy (i, j; k , l ) are
linear voltage controlled current sources
with the characteristics which
I xy (i, j; k , l ) = A(i, j; k , l )V ykl
(1)
and
I xu (i, j; k , l ) = B(i, j; k , l )Vukl .
(2)
I yx 
1
R y ( Vxij  1  Vxij  1 )
2
(3)
is a piecewise-linear voltage controlled
current source; Eij
is a time-invariant
independent voltage source.
The circuit equations of a cell which satisfy
KCL and KVL are easily derived as follow:
State equation is
C

dVxij (t )
dt

1
Vxij (t )
Rx
 A(i, j; k , l )V
ykl
(t )
ukl
(t )  I .
C ( k ,l )N ( i , j )

 B(i, j; k , l )V
C ( k ,l )N ( i , j )
(4)
II. The Λ-type NDR Device
A Λ-type MOS-NDR device is composed of
three NMOS transistors. This circuit is shown
in figure 2. In the region 2, VDS exceeds the
threshold voltage of Q3 and Q3 changes from
cutoff state to saturation state. In the
meanwhile, VGS will go down and current
from drain to source of Q2 also goes down.
This is the reason why there is a negative
differential resistance in the region 2.
Where A(i, j; k , l ) and B (i, j; k , l ) are the
nonlinear cloning templates.
Output equation is
V yij (t ) 


1
Vxij (t )  1  Vxij (t )  1 .
2
(5)
Input equation is
Vuij  Eij .
(6)
Constraint conditions are
Vxij (0)  1, Vuij  1 .
Parameter assumptions are
A(i, j; k , l )  A( k , l ; i, j ),
(7)
Fig. 2. A Λ-type NDR device circuit is
composed of three NMOS.
(8)
where 1  (i, k )  M , 1   j, l   N and
N (i, j ) is the neighbor set of C (i , j ) .
The Λ-type I-V characteristics and the
operation point are shown in figure 3 and
table1 of each transistor.
I
(1)
(2)
(3)
V
Fig.1. It is an example of a cell circuit.
VDS
Q1
Q2
Q3
VDS < VT
Saturation
Linear
Cut-off
VDS = VGS +VT
Saturation
Linear→ Saturation
Saturation
VGS≤VDS+VT
Saturation
Linear
Saturation
Fig.3. It is the I-V curve of Λ-type.
Table 1. This table shows the operating point
of each transistor for a NDR device.
suitably
determining
the
parameters
of
III. The Inverter based on Λ-type NDR Device
devices and circuits, figure 6 shows the
simulated results for the inverter.
The inverter is constructed by a NMOS
device and a MOS-NDR device which are
connected parallel. The total current Itotal is
the sum of the currents flowed through the
MOS-NDR and NMOS devices : Itotal = INDR +
IMOS. Since IMOS can be modulated by the gate
voltage (VG), so is Itotal, as show in figure 4.
Fig. 5. Inverter circuit design based on the
MOBILE.
Fig.4. The peak current of Λ-type MOS-NDR
device can be controlled by the VG voltage.
Our inverter circuit design is based on two
series-connected MOS-NDR devices as
shown in figure 5. This circuit is so called the
monostable-bistable transition logic element
(MOBILE). The input node is located at the
VG gate. The output node is located between
the two MOS-NDR devices. When the bias VS
Fig. 6. These are the simulated results for the
inverter.
is bigger than twice peak voltage (2VP), but is
smaller than twice valley voltage (2VV), there
is two possible stable points (bistable) that
respect the low and high states (corresponding
to “0” and “1”), respectively. A small
difference between the peak currents of the
series-connected NDR devices determines the
state which the circuit will stay stably. By
MOBILE at the output is show in Fig 7.The
IV. The MOBILE CNN
The cell circuit configuration of a DT-CNN
implemented with MOBILE’s. Here, the cell
with positive feedback and an inverting
state of MOBILE are clocked with the VA
clock, the states of inverter are clocked with
the VB clock. VA and VB are complementary
clocks. Hence, the output A is complementary
with output B. The cell outputs with clock are
on the control. Since output values can be
latched when clock is high and is changeable
when clock is low. The cell circuit is
evaluation of the output voltage of the cells.
controlled and driven by input, self-feedback
and clock. The cell can adjust branch in
parallel with the loading MOS-NDR to
generate different outputs. The simulating
results of the DT-CNN are shown in the
figure 8. We can see the outputs of cells will
remain stably only within a few iterative
process. The cell of DT-CNN based on MOSNDR device is as good as RTD-based cell. It
also can be manufactured by stand CMOS
The evaluation of the cell’s states was
illustrated schematically in the upper inset.
Here, the black pixels indicated cell state is 1
and white pixels indicated cell state is 0.
process.
process. The I-V characteristics of the NDR
device could be controlled by the Vg voltage.
Hence, it is easier to control than RTD
VA
VB
VA
cellular
on the
circuits
CMOS
DT-CNN.
outputA
O
u
t
V. Conclusions
We have designed a discrete-time
neural network (DT-CNN) based
Λ-type NDR-based devices and
according to the standard 0.35μm
outputB
O
References
Input from
1. L.O. Chua and L. Yang ,“Cellular Neural
the neighboring
Networks ： Theory”, IEEE Transactions on
cells
p
u
Fig.7
It is the circuital configuration of
t
DT-CNN
implemented with MOBILE’s. A
A
cell consists with positive feedback and
inverting MOBILE at the output.
Fig. 8. These are simulating results for the
DT-CNN. The traces show the time
circuits and systems, vol.35, no.10, pp.1257
-1272, October 1988.
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November 1991
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