Download II. MOS-NDR Device and Inverter DESIGN

Novel Voltage-Controlled Oscillator Design by
MOS-NDR Devices and Circuits
Dong-Shong Liang*, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen,
Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, and Long-Xian Su
Department of Electronic Engineering, Kun Shan University of Technology, Taiwan, R.O.C.
Abstract--This paper describes the design of a
voltage-controlled oscillator (VCO) based on the negative
differential resistance (NDR) devices. The NDR devices used in
the work is fully composed by the metal-oxide- semiconductor
field-effect-transistor (MOS) devices. This MOS-NDR device
can exhibit the NDR characteristic in its current-voltage curve
by suitably arranging MOS parameters. The VCO is
constructed by three low-power MOS-NDR inverter. This
novel VCO has a range of operation frequency from 151MHz
to 268MHz. It consumes 24.5mW in its central frequency of
260MHz using a 2V power supply. This VCO is fabricated by
0.35μm CMOS process and occupied an area of 120 x 86 μm2.
the Λ-type NDR I-V characteristic by suitably arranging the
MOS parameters. Figure 2 shows the I-V curve, measured
by Tektronix-370B curve trace, with the width parameters
of the three MOS devices as 1μm, 10μm, and 40μm,
respectively. The MOS length is fixed at 0.35μm. The VGG
is fixed at 3.3V.
I. INTRODUCTION
II. MOS-NDR DEVICE AND INVERTER DESIGN
Figure 1 shows a MOS-NDR device which is
composed of three NMOS transistors. This circuit can show
Fig. 1 The circuit configuration of a Λ-type MOS-NDR
device.
2
W1=1u,W2=10u,W3=40u
VGG=3.3V
1.6
Current(mA)
In recent years, several new applications based on
resonant tunneling diode (RTD) have been reported [1]-[4].
The negative-differential-resistance (NDR) current-voltage
(I-V) characteristics of the RTD devices have several
advantages, and they may have high potential as functional
devices due to their unique folding I-V characteristics.
However these RTD devices are fabricated by the
compound semiconductor and process. Therefore this kind
of NDR device is difficult to combine with other devices
and circuits to achieve the system-on-a-chip (SoC).
Therefore, we proposed a new MOS-NDR device that
is fully composed of metal-oxide-semiconductor
field-effect-transistor (MOS) devices. During suitably
arranging the MOS parameters, we can obtain the NDR
characteristic in its I-V curve. We call this NDR device as
MOS-NDR device. Because this NDR device is consisted
of the MOS devices, yet it is much more convenient to
combine other devices and circuits to achieve the SoC by
standard CMOS process.
We will demonstrate a novel voltage-controlled
oscillator (VCO) designed based on the MOS-NDR devices
and circuit. The VCO is constructed by three cascading
low-power MOS-NDR inverters. The basic inverter is
composed by two series-connected MOS-NDR devices
according to the monostable-bistable transition logic
element (MOBILE). The signal will be feedback from the
output of the third MOS-NDR inverter to the input of the
first MOS-NDR inverter. Under suitable design, we can
obtain an oscillator with its frequency proportional to the
magnitude of input bias. We design and implement this
VCO by the 0.35μm CMOS process.
(2)
(1)
(3)
(4)
1.2
0.8
0.4
0
0
0.5
1
1.5
2
2.5
Voltage(V)
Fig. 2 The measured I-V characteristic for a MOS-NDR
device..
If we connect a NMOS with a MOS-NDR device in
parallel, we can modulate the peak current of MOS-NDR
device’s I-V curve through the gate voltage of NMOS. The
circuit is shown in Fig. 3. The total current ITotal is the sum
of the currents through the MOS-NDR and NMOS devices:
ITotal=INDR+IMOS. Since IMOS is modulated by the gate
voltage (VG), so is ITotal. Our inverter circuit design is based
on two series-connected MOS-NDR devices as shown in
Fig. 4. This circuit is called as monostable-bistable
transition logic element (MOBILE) [5]-[6]. The input node
is located at the VG gate. The output node is located
between the two MOS-NDR devices. When the bias voltage
is smaller than twice the peak voltage (2VP), there is one
stable point (monostable) in the series circuit.
However when the bias voltage is larger than two peak
voltages but smaller than two valley voltages (2VV), there
will be two possible stable points (bistable). The
intersection point located at the NDR region for two I-V
curve will be regarded as unstable point. The two stable
points that respect the low and high states (corresponding to
“0” and “1”), respectively, are shown in Fig. 5. A small
difference between the peak currents of the two devices
determines the state of the circuit. If the peak current of the
driver device is smaller than that of the load device, the
operation point will be located at the high state. On the
other hand, if the peak current of the driver device is bigger
than that of the load device through the VG voltage, the
operation point will be located at the low state.
Fig. 5 The bistable states when VS is bigger than2VP but
smaller than 2VV.
By suitably determining the parameters of devices and
circuits, we can obtain the inverter result as shown in Fig. 6.
Figure 7 illustrates the relationship between the input bias
VS and the power dissipation for a MOS-NDR inverter. The
power dissipation of this inverter is 5.75mW using a 2V
power supply.
Fig. 3 The peak current of MOS-NDR device can be
controlled by the VG voltage.
Fig. 6 The MOS-NDR inverter result.
Fig. 4 The MOS-NDR inverter designed by MOBILE
theory.
Power Dissipation (mW)
10
8
6
4
2
0
1.6
2
2.4
Input Bias (V)
Fig. 7 The power dissipation for a MOS-NDR inverter.
III. VCO DESIGN
The circuit configuration of the novel VCO is shown
in Fig. 8. The oscillator circuit is composed of three
cascading MOS-NDR inverters. The signal will be feedback
from the output of the third MOS-NDR inverter to the input
of the first MOS-NDR inverter. This VCO is designed and
fabricated by the standard 0.35μm CMOS process and
occupied an area of 120 x 86 μm2. Figure 9 shows the
layout of VCO.
Fig. 10 The simulated waveform of the oscillator.
Fig. 11 The simulated waveform of the oscillator.
Fig. 8 The circuit configuration of the VCO.
Frequency (MHz)
280
240
200
160
120
1.6
2
2.4
Input Bias (V)
Fig. 12 The relationship between the input bias and the
oscillation frequency.
Fig. 9 The layout of VCO.
IV. SIMULATION RESULTS
Under suitable parameters design, we can obtain an
oscillator with its frequency proportional to the magnitude
of input bias VS. Figure 10 shows the simulated waveform
of the oscillator under 2V bias voltage by HSPICE program.
Figure 11 shows its spectrum.
Figure 12 illustrates the relationship between the input
bias and the oscillation frequency. This VCO has a range of
operation frequency from 151MHz to 268MHz. The
relationship between the power dissipation and input bias is
shown in Fig. 13. It consumes 24.5mW in its central
frequency of 260MHz using a 2V power supply.
Power Dissipation (mW)
40
30
20
10
0
1.6
2
Input Bias (V)
Fig. 13 The power dissipation for a VCO.
2.4
V. Conclusions
We have designed a voltage-controlled oscillator
(VCO) based on the Λ-type MOS-NDR devices and circuits.
The VCO is composed of three cascading low-power
MOS-NDR inverters. For chip area die consideration, we
use fully MOS devices instead of LC-tank structure. The
oscillation frequency is from 151MHz to 268MHz. This
VCO is designed by the standard 0.35μm CMOS process. If
we fabricated this VCO by 0.18μm CMOS process, the
oscillation frequency will be increased above GHz.
[2]
[3]
[4]
ACKNOWLEDGMENTS
The authors would like to thank the Chip
Implementation Center (CIC) of Taiwan for their great
effort and assistance in arranging the fabrication of this chip.
This work was supported by the National Science Council
of Republic of China under the contract no. NSC93-2218E-168-002.
[5]
[6]
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