Download Multichip module with planar-integrated free-space

Multichip module with planar-integrated free-space
optical vector-matrix-type interconnects
Matthias Gruber
Even in the semiconductor industry, free-space optical technology is nowadays seen as a prime option for
solving the continually aggravating problem with VLSI chips, namely, that the interconnect technology
has failed to keep pace with the increase in communication volume. To make free-space optics compatible with established lithography-based design and fabrication techniques the concept of planar
integration was proposed approximately a decade ago. Here its evolution into a photonic microsystems
engineering concept is described. For demonstration, a multichip module with planar-integrated freespace optical vector-matrix-type interconnects was designed and built. It contains flip-chip-bonded
vertical-cavity surface emitting laser arrays and a hybrid chip with an array of multiple-quantum-well
p–i–n diodes on top of a standard complementary metal-oxide semiconductor circuit as key optoelectronic
hardware components. The optical system is integrated into a handy fused-silica substrate and fabricated with surface-relief diffractive phase elements. It has been optimized for the given geometrical and
technological constraints and provides a good interconnection performance, as was verified in computer
simulations on the basis of ray tracing and in practical experiments. © 2004 Optical Society of America
OCIS codes: 200.4650, 200.4860, 050.1380, 220.0220.
1. Introduction
In information technology three main tasks can be
distinguished: transmission, processing, and storage of data. All three of these tasks used to be carried out at the beginning of the modern information
age almost exclusively by means of electrical and
electronic devices. Such was the case for data processing until recently, and because there is no alternative in sight that can compete with very-large-scale
integrated 共VLSI兲 complementary metal-oxide semiconductor 共CMOS兲 technology and its highly sophisticated design and fabrication methods, electrical
technology will certainly continue to dominate data
processing for the foreseeable future.
The situation is different for data storage and
transmission. In these fields optics has evolved as a
strong competitor for electronics. Nowadays every
computer is equipped with a CD or DVD drive, and
the corresponding storage media have become industrial mainstream products. In commercial data
transmission systems, whether optical or electronic
The author 共[email protected]兲 is with the Lehrgebiet Optische Nachrichtentechnik, Fern Universität Hagen, Universitätsstrasse 27, 58084 Hagen, Germany.
Received 22 March 2003.
0003-6935兾04兾020463-08$15.00兾0
© 2004 Optical Society of America
technology is employed depends on the distance between source and destination. On the one hand optics has many fundamental advantages in terms of
bandwidth, suitability for multiplexing, low cross
talk, immunity from electromagnetic interference,
distance scalability, and less power consumption.1
On the other hand optical data transmission requires
optoelectronic conversion stages and a more complex
fabrication technology, which has an increasingly penalizing effect the shorter the transmission distance
gets. This and the relative immaturity of industrialscale optical interconnect technology has so far prevented the use of optics from gaining substantial
ground in the realm of short-distance interconnects.
However, this situation is about to change, driven
by what is sometimes called the interconnect crisis of
VLSI electronics. This means that the current interconnect technology, which is planar in essence, can
no longer keep up with the increase in communication volume because the interconnection capacity
scales only linearly with fabrication technology
whereas the demand grows overlinearly according to
Rent’s rule. After more than three decades of exponential growth of the processing power of integrated
circuits, following Moore’s law a huge gap has opened
between communication demand and potential. In
integrated circuits with integration densities of the
order of 107 transistors兾mm2 for microprocessor
chips 共and even five times higher for memory chips兲
10 January 2004 兾 Vol. 43, No. 2 兾 APPLIED OPTICS
463
and operating at clock speeds near 10 GHz that the
semiconductor industry has on its agenda, the interconnection problem cannot be solved adequately with
current electrical approaches, as the recent Semiconductor Industry Association road maps clearly point
out.2
Research on short-range optical interconnects covers a wide range of approaches 共see, for example,
Refs. 3 and 4兲. One main direction for research is
the extension of guided-wave optics to shorter domains. It includes the use of fibers between printedcircuit boards and of waveguides between and on
chips as well as the exploration of waveguide structures in photonic-crystal materials. The other main
direction is free-space optics. It has the particular
advantage of yielding truly three-dimensional and
hence scale-proof interconnect architectures in a
quite natural way and with comparatively simple
hardware. The inherent spatial parallelism of freespace optics, which easily supports channel densities
of the order of 103兾mm2, ideally matches the requirements of the short-range interconnect domain.
The challenge with free-space optical interconnects
lies in the need to go beyond a mere miniaturization
of classical setups made from discrete components
and to establish integrated system and packaging
concepts that are compatible with mainstream VLSI
technology.5,6 Three basic free-space optical integration concepts have been introduced during the
past 20 years7–9; one of them, planar integration, is
the basis for this paper. Its evolution into a planar
photonic system technology that comprises free-space
and fiber-optical, optoelectronic, and electrical components is described. For practical demonstration a
multichip module 共MCM兲 with optical vector-matrixtype interconnects was designed and built. This
type of module has fundamental importance for optical cross-connect switches and for parallel optical
computing architectures.
In Section 2 the idea of planar free-space optics is
briefly recalled, and the current status of planarintegrated photonic integration is laid out. In Section
3 the architecture of the demonstrator MCM is presented, and key optoelectronic hardware components
共optoelectronic–VLSI chips兲 are described. In Section
4 I deal with the optical system’s design and its performance in computer simulations. Fabrication and
assembly issues are discussed in Section 5, and the
experiments with the finished MCM are described.
In the concluding Section 6, future research directions
in the field of planar photonic integration are sketched
and potential commercial applications are pointed out.
2. Planar-Integrated Photonic Systems
For VLSI electronics a rich pool of highly sophisticated and extremely accurate design and fabrication
techniques has been developed over the past half century. The main characteristics of these techniques
are the use of a planar substrate 共wafer兲 as a system
platform and of lithography 共mask-based approach兲
for system replication. To make free-space optics
464
APPLIED OPTICS 兾 Vol. 43, No. 2 兾 10 January 2004
Fig. 1. Schematic drawing that shows the current level of development of planar-integrated photonic microsystems.
compatible with these techniques, the concept of planar integration was invented.9,10
The idea is to use an entirely analogous system
approach by integrating a classical optical laboratory
setup into a planar substrate with a thickness of the
order of millimeters and a diameter of the order of
centimeters. This is done by miniaturizing and folding the setup such that optical signals travel along
zigzag paths inside the substrate and all optical components fall onto the substrate’s plane-parallel surfaces 共Fig. 1兲. Passive components can thus be
implemented conveniently through surface-relief
structuring or spatial index modulation by use of
mask-based techniques.11,12 Active components can
be attached to the substrate surfaces by microassembly techniques such as flip-chip bonding. Signal
propagation inside the substrate requires transparent materials such as optical glasses or plastics; however, because optical data communication takes place
mostly in the infrared wavelength range, classical
semiconductor materials are often also suitable.
The appeal of the planar integration approach to
system design lies in the fact that optical system
architectures remain fully three-dimensional, thus
facilitating complex and densely packed communication and interconnect schemes,13,14 whereas the fabrication methods become two dimensional, with the
benefit of considerably reduced complexity. Another
advantage is the high robustness that one obtains by
confining the optical communication inside the substrate and thus shielding it from environmental influences. Although such confinement could in
principle be achieved on the basis of total internal
reflection, it is more practical for most applications to
avoid the related geometrical constraints and to use
reflective coatings instead.
After more than a decade of research, planar integration has meanwhile evolved into a photonic packaging concept that encompasses all facets of modern
microsystems engineering. The transparent substrate can be seen as the multifunctional backbone of
such a photonic module. In addition to housing the
free-space optical system it can serve as a board for
printed electrical circuits and carry optoelectronic
and optomechanic chips.15,16 At the same time it
may take over thermal functions such as heat spreading.17 Planar-integrated optoelectronic MCMs are
undoubtedly ideal for handling massively parallel
short-range communication; however, for the
medium- and long-range domain fiber-based hardware is more practical. To make both communication concepts compatible a fiber free-space optical
interface was developed that allows one to couple
optical signals conveniently and reliably between
fiber bundles with MT-type connectors and planarintegrated free-space systems.18 Figure 1 schematically summarizes the current experimental level of
development of such photonic microsystems.
At this point it is interesting to note that some
important trends in photonics in the past decade are
quite favorable for planar integration. For example,
under system aspects semiconductor light sources
that emit perpendicularly to the chip surface are
desirable; vertical-cavity surface-emitting laser
共VCSEL兲 diodes, which are currently the focus of intensive research, are therefore ideal. Issues such as
energetic efficiency and thermal management can
nowadays be controlled so well in these devices that
one- and two-dimensional arrays with packaging
densities of the order of hundreds per square millimeter are feasible.19 High integration densities
have also been demonstrated for modulator arrays.
Prominent examples of such arrays are hybrid Si–
GaAs compound chips with arrays of multiplequantum-well 共MQW兲 p–i–n diodes on top of CMOS
circuits20; such devices have the potential to handle
modulation frequencies in the gigahertz range and
an aggregate data throughput of many terabits per
second.21,22 These trends lead to the conclusion
that optoelectronic–VLSI chips with optical input–
output arrays that are distributed across the entire
chip area and possibly organized in accordance with
a so-called smart-pixel concept combined with
planar-integrated free-space optical interconnection
systems are a practical solution to the so-called interconnect crisis.
Furthermore, the progress that has been made in
integrating electronic and optoelectronic circuits on
insulating wafer materials is noteworthy. With a
commercial technique termed ultrathin silicon on
sapphire23 it is possible to produce integrated circuits
with desirable electrical properties such as an extremely low cross talk and the useful optical property
of being transparent for the whole visible and nearinfrared wavelength range. This property allows
one access to optical input– output arrays conveniently from both sides of the wafer and thus makes
possible compact and versatile planar-integrated
photonic modules.
In Section 3 the aforementioned ideas are applied
for the design of a compact optoelectronic MCM with
vector-matrix-type free-space optical interconnects.
3. Planar-Integrated Vector-Matrix Architecture
Vector-matrix 共VM兲 type architectures are a suitable
object of investigation for two reasons. First, they
are of fundamental importance for optical switching
Fig. 2. VM-type optical interconnects implemented by means of
two anamorphic imaging stages 共here depicted as cylindrical
lenses兲.
and computing. As components of switching hardware they are usually called cross connects and are
attractive because they have low latency, are strictly
nonblocking, and do not require sophisticated control
and configuration algorithms. Their relevance for
digital computing lies in the fact that any digital
algorithm may be executed in parallel by use of appropriate sets of Boolean sum-of-product terms of the
given input data that can be calculated through binary VM multiplications.24 And in the field of analog computing we find that all one-stage neural
networks essentially also carry out a generic VM multiplication.25
Second, VM-type architectures involve point-tomultipoint 共fan-out兲 and multipoint-to-point 共fan-in兲
operations that cannot so easily be achieved with
electronic or guided-wave optical hardware if the
splitting or combining ratio is high.1 By contrast,
elegant and comparatively simple implementations
are possible with free-space optics; the latter approach also supports large fan-out and fan-in. Most
well known is the type of optical setup pioneered by
Goodman et al.26 that is shown schematically in Fig.
2. It is based on two anamorphic imaging stages
共depicted as cylindrical lenses兲 with orthogonal orientation. Signals from the one-dimensional emitter
array representing input vector u are fanned out and
modulated by the two-dimensional array representing matrix w; the resultant product terms wijuj are
then superimposed by the fan-in stage onto the onedimensional detector array representing output vector v to implement the summations of the operation
vi ⫽ ¥ wijuj . Practical instances and variations of
this generic setup, which include an extension to twodimensional input– output arrays, were studied by
various groups of researchers.27–29 Possibilities for
its planar integration have been discussed as well.30
Here one possible planar system approach is developed into an optoelectronic MCM with VM-type interconnection and optical programming of the matrix.
From the schematic of Fig. 3 it can be seen that the
module contains a folded version of the basic setup of
Fig. 2 along the x direction; this subsystem implements the optical VM multiplication. The programming is based on an outer-product-addressing
scheme and carried out by means of the fan-out part
of the subsystem just mentioned and by a second,
essentially identical, fan-out stage along the y direction. The module is composed of two transparent
substrates: a thinner one, labeled electrical, that
10 January 2004 兾 Vol. 43, No. 2 兾 APPLIED OPTICS
465
Fig. 4. Micrograph of the hybrid modulator chip that was later
bonded onto the electrical substrate of the MCM.
Fig. 3. Schematic of the optoelectronic MCM with a planarintegrated version of the VM-type interconnects of Fig. 2 and a
second optical fan-out stage for optical programming of the modulator chip.
serves as a board for the electrical lines 共not shown in
Fig. 3兲 and for four optoelectronic chips, and a thicker
one, labeled optical, that essentially contains the
whole planar-integrated free-space optical interconnect system. In this demonstrator all optical components are to be implemented as diffractive phase
elements 共DPEs兲 and fabricated by lithographic
surface-relief structuring.
The types of signal sources that are most suitable
for such a MCM are one-dimensional arrays of VCSEL
diodes; photodiode arrays are ideal for detection.
Both device types are nowadays readily available as
unpackaged chips. A little more tricky is the choice
of a device that represents the matrix, because there
are two fundamental options. One is to use genuine
optical modulators such as the MQW-p–i–n diodes
mentioned in Section 2 that can be arranged in twodimensional arrays and hybridly integrated with
CMOS chips; the other is based on smart pixels consisting of a detector, a VCSEL, and an electrical circuit that modulates the VCSEL according to the
detected optical signal. The second option provides
much higher contrast but it is more problematic in
terms of the thermal management. Currently the
most important decision criterion, however, may
共still兲 be availability.
For this research the first option was chosen because a hybrid modulator chip was conveniently
available through the Consortium for Optical and
Optoelectronic Technologies in Computing 共CO-OP兲
program.31 An array of 20 ⫻ 10 MQW p–i–n diodes
with a pitch of 62.5 ␮m ⫻ 125 ␮m could be combined
with a CMOS circuit of arbitrary, customer-defined
functionality. Our chip was designed in cooperation
with two other research groups15 and is organized as
a 10 ⫻ 10 array of smart pixels. One of the two
MQW p–i–n diodes that belongs to each pixel is operated as a detector and used to optically program the
state of that matrix element. The other diode is operated as a reflective absorption modulator and is
466
APPLIED OPTICS 兾 Vol. 43, No. 2 兾 10 January 2004
used for the optical VM multiplication. Figure 4
shows the optical interface side of the smart-pixel chip
that was later bonded onto the electrical substrate.
The basic functionality of the component was successfully verified before its assembly through tests in
a probe station. In Fig. 5 an electrical control signal
共top兲 and the resultant optical modulation 共bottom兲 at
a frequency of 20 MHz are plotted. With the given
electronic circuitry and measurement equipment a
maximum modulation frequency of ⬃100 MHz could
be demonstrated. Computer simulations suggest
that this value could be boosted to at least 400 MHz
with an optimized CMOS chip layout.
After this discussion of the hardware on the electrical substrate, in Section 4 we shall concentrate on
the optical substrate. A detailed description of the
free-space optical interconnects will be provided.
4. Optical System Design
The optical system design for the MCM of Fig. 3
combines features of two key predecessor implementations. From Ref. 26 the anamorphic imaging approach is adopted for the optical fan-in. The idea is
to achieve a large demagnification in the y direction
along which the matrix elements are to be summed
共cf. Fig. 2兲 while maintaining the scale in the orthogonal direction. In this way a linear array of optical
signals can be compressed into a spot with 共nearly兲
equal extension in x and y and thus be superimposed
Fig. 5. Performance of a MQW p–i–n diode operated as an optical
modulator in a test before bonding of the chip. 共Courtesy of L.
Hoppe, Institute for Physical High Technology, Jena, Germany.兲
Table 1. Focal Lengths in the x–z- and the y–z Cross Sections,
Dimensions, and Center Positions of the Optical Elements Depicted in
Fig. 6a
Optical
Element
fx
fy
Dx
Dy
x
E
L1
BS
L2
L3
L4
L5
41 448
⬁
40 594
18 620
18 620
⫺280 858
18 620
40 854
⫺71 822
28 700
20 928
18 035
⫺16 000
12 259
500
1000
1682
3000
3000
1900
3000
3000
2500
2700
2500
4000
2500
3476
⫺10 083
⫺7 583
⫺5 083
⫺2 583
2 583
5 083
7 583
All numbers are in micrometers. y ⫽ 0 in all cases.
a
Fig. 6. Components of the optical fan-out and fan-in stages and
their functions in the two principal cross sections.
onto a standard detector element. From Ref. 30 the
idea of obtaining the optical fan-out through multiple
imaging with the aid of diffractive beam splitter gratings is adopted. Compared with anamorphic imaging, this approach is much more efficient if there is a
significant amount of dead space between the matrix
elements as is the case with the modulator elements
on the CO-OP chip.
In contrast to the study reported in Ref. 30, however, here the optical fan-out stages are composed of
three elements instead of only one. This configuration provides a considerably larger number of design
parameters, which are utilized to compensate for optical aberrations and for the geometrical constraints
imposed by the fact that optical elements need to be
integrated into the substrate surfaces. For the analysis and synthesis of an optical system that is not
circularly symmetric it is helpful to separate the system’s functionality with respect to the directions of
the principal axes. In our case this leads to the two
system projections depicted in Fig. 6. Note that in
this design optical elements that require a surface
relief are located solely at the top surface of the optical substrate, thus reducing fabrication complexity.
The plane mirrors of the bottom surface are omitted
in Fig. 6. Also note that the pictorial symbols for the
DPEs are chosen such that they suggest the respective phase-modulation properties.
The fan-out stage consists of four elements. Lens
E deflects the incoming optical signals onto their zigzag paths and ensures object–side telecentricity; because of its proximity to the VCSELs it has little
influence on the actual imaging operation. Elements L1, BS, and L2 act as pure lenses in the y–zcross section and are optimized for skew beam
passage32 to produce distortion- and astigmatismfree imaging onto the modulator plane with a magnification of m ⫽ ⫺0.5. Note that lens L1 has
negative focusing power, which is reminiscent of a
photographic wide-angle lens assembly. In the x–z
cross section, L1 has no optical function, whereas
beam splitter BS combines the functions of a lens and
a diffractive 1 ⫻ 10 beam splitter grating. For the
latter functionality the same phase delay function as
described in Ref. 30 is employed; it was generated by
means of an iterative Fourier-transform algorithm.33
Together with lens L2 an array of 10 telecentric image
spots is thus generated in the modulator plane.
The fan-in stage consists of three elements, L3, L4,
and L5, which act as pure lenses. The distribution of
focusing power, however, is different in the two projections to implement different magnifications; in the
x–z cross section it is m ⫽ ⫺1, whereas it is m ⫽ ⫺0.5
in the y–z cross section. Ideally the latter number
should be much closer to zero, but technological constraints imposed by our clean-room facilities prevent
the fabrication of the faster lenses that would be
needed to achieve a stronger anamorphism. Like its
counterpart for fan-out, the fan-in imaging system
has been corrected with respect to distortion and
astigmatism. The other third-order aberrations can
be neglected because they are not critical at the comparatively low numerical aperture of 0.046. More
details of the optical parameters of the DPEs are
listed in Table 1.
The quality of the optical interconnect system was
tested in computer simulations on the basis of ray
tracing. Thereby all crucial performance requirements could be confirmed. Figure 7 shows exemplarily three viewing perspectives of two simulations
of the optical fan-out stage, one with an on-axis, the
other with an off-axis light source. The numerical
evaluation of the resultant spot images 共Fig. 8兲 revealed that no spot center falls more than 1 ␮m off its
target position and that spot diameters are of the
order of 10 ␮m, which is sufficient for reliably addressing the 20 ␮m ⫻ 20 ␮m large optical windows of
the MQW p–i–n diodes 共note that almost all computed rays hit ideally positioned target areas of this
size兲. The observed shape of the spot images can be
attributed mainly to residual coma.
5. Fabrication, Assembly, and Testing
The optical system described in Section 4 was fabricated upon a 9-mm-thick fused-silica substrate with a
50.8-mm diameter by use of three subsequent steps of
binary lithography and reactive ion etching. The
resultant DPEs contain eight equidistant phase delay levels in the interval 关0, 2␲兴 and can therefore
achieve a maximum diffraction efficiency of ⬃95%.
Reflective coatings were applied by physical vapor
10 January 2004 兾 Vol. 43, No. 2 兾 APPLIED OPTICS
467
Fig. 7. Pseudo-three-dimensional and top views of ray tracing simulations of the fan-out stage with an on-axis and an off-axis signal
source.
deposition of aluminum. The finished optical substrate for the experiments is shown in Fig. 9共a兲.
Figure 9共b兲 shows the finished electrical demonstrator substrate, which has a thickness of 0.5 mm.
The electrical lines on it are thin compound films of
titanium, palladium, and gold and were applied
through physical vapor deposition as well. After
that the two VCSEL chips and the hybrid modulator
chip were flip-chip bonded at their respective positions. The place for the detector chip was left empty
because in the first laboratory experiments I intended to use a CCD camera for optical evaluation of
the output signals.
Unfortunately it turned out at this point that only
the two VCSEL chips worked properly 共cf. Fig. 10兲,
whereas the modulator chip 共the sole chip available
for flip-chip bonding兲 did not respond to control signals. Figure 4 gives rise to the suggestion that bad
electrical contacts might be the reason. A substitute
chip in the form of a small glass plate with an array
of evaporated micromirrors was produced to permit
some optical experiments still to be carried out.
These mirrors have the same size and pitch as the
optical windows of the MQW p–i–n diodes and are
assumed to simulate one particular 共fixed兲 constellation of the switching matrix. A second electrical
substrate was then prepared and populated with this
chip substitute and a second set of VCSEL chips.
Precise alignment of the electrical and the optical
substrates was achieved by means of a technique
based on optical imaging of special alignment marks
onto themselves.34 The fully aligned test setup is
shown in Fig. 11. To my knowledge it is the first
practical demonstration of a planar-integrated photonic module with electrical, optoelectronic, and freespace optical microcomponents. Note that one of the
VCSELs is being addressed electrically with probe
needles in Fig. 11.
Optical tests were carried out with the second, substitute, electrical substrate. In one experiment a
CCD camera was focused onto the micromirror array
from the electrical side of the setup. Inasmuch as
the aluminum film of these mirrors was kept thin
enough to make the mirrors semitransparent, one
Fig. 8. Spot patterns obtained from the simulations shown in Fig.
7 for signals 共I兲–共IV兲. Filled squares, the size and ideal position of
the respective modulator elements.
Fig. 10. One of the bonded VCSEL chips viewed through the
electrical substrate. In the blowup, one of the VCSELs is
switched on and emits light with a wavelength of 850 nm.
468
APPLIED OPTICS 兾 Vol. 43, No. 2 兾 10 January 2004
Fig. 9. 共a兲 Optical substrate of the MCM mounted for experimental tests. 共b兲 Fully populated electrical substrate of the MCM; for
better mechanical stability the optoelectronic chips were fixed with
glue in addition to flip-chip bonding.
␮m is still less than the dimensions of most commercial detector elements, such a focusing error could
likely be tolerated in practice.
6. Conclusions
Fig. 11. Fully assembled experimental demonstrator of the optoelectronic MCM with VM-type optical interconnects.
can conveniently observe the mirror array and visually evaluate the position and quality of the 10 replicated spots. Figure 12 illustrates such an
experiment; here every second mirror in the third row
from the top is addressed. The blow-up at the right
clearly shows that the spots hit their targets well. A
quantitative evaluation of these spots yielded an average diameter of 10.1 ␮m FWHM, which agrees well
with theoretical expectations.
In another experiment the camera was focused
onto the output area to facilitate a similar spot evaluation for optical fan-in. The average spot diameter
was 24 ␮m in this case, which was approximately
twice the theoretically expected dimension and can
be attributed to a slight mismatch of the image plane
and the detector plane. Nevertheless, because 24
In this paper the evolution of the planar integration
concept for free-space optics into a planar-integrated
photonic system engineering concept has been described. This approach is supported by the technological progress that has been achieved with key
optoelectronic hardware such as arrays of VCSELs
and MQW p–i–n diodes and by novel technologies
such as ultrathin silicon-on-sapphire. For demonstration a planar-integrated MCM with vectormatrix-type optical interconnects was designed and
fabricated. The MCM is believed to be the first
module of its kind that integrates electrical, optoelectronic, and optical microcomponents. The functionality of the optical interconnects was successfully
demonstrated.
The main weakness of this test module 共and of
most predecessor systems兲 is the low coupling efficiency of ⫺20 to ⫺10 dB that is currently achieved.
There are two important reasons for this low efficiency: the use of a cheap and easy-to-handle but
rather low-reflective coating material 共aluminum兲
and the use of staircase-type DPEs, which suffer from
substantial diffraction losses. However, both problems can be solved rather straightforwardly by the
use of different coating materials such as dielectrics
and of different types of optical components, for example, refractive optical elements that are fabricated
by analog lithography.
Solution of these problems will be one focus of my
future research. Another will be the continued expansion of the planar-integrated photonic system
concept. In connection with a European Union–
sponsored research project, the High-Speed Optoelectronic Memory System 共HOLMS兲,35 efforts are
currently under way to laminate electrical circuits
Fig. 12. Experimental demonstration of the optical fan-out. The optical signals exactly hit their respective targets, in this case
semitransparent micromirrors of size 20 ␮m ⫻ 20 ␮m.
10 January 2004 兾 Vol. 43, No. 2 兾 APPLIED OPTICS
469
onto planar-optical substrates and to develop an optical interface between planar-integrated free-space
optics and waveguides that are embedded in conventional printed-circuit boards.
The HOLMS project aims at providing the means
to reduce the latency in the processor–memory communication that has been identified as the main limitation on the computing power of contemporary
multiprocessor systems. In this field planarintegrated photonic systems may find commercial applications in the near future. Another application
with high commercial relevance is optical clock distribution for high-speed VLSI chips. Here the high
spatial parallelisms provided by free-space optics and
the compact size and robustness of a planarintegrated module are highly desirable.
The author thanks Jürgen Jahns for initiating this
interesting research topic as well as Stefan Sinzinger,
Detlev Hagedorn, Dietmar Fey, Guido Grimm, and
Lutz Hoppe for helpful discussions and practical assistance. Funding from the Stiftung Volkswagenwerk, Germany, is gratefully acknowledged.
References
1. D. A. B. Miller, “Physical reasons for optical interconnection,”
Int. J. Optoelectron. 11, 155–168 共1997兲.
2. For the International Technology Roadmap for Semiconductors, see http:兾兾public.itrs.net兾.
3. Y. Lee, E. Towe, and M. W. Haney, eds., issue on optical
interconnections for digital systems, Proc. IEEE 88, 723– 863
共2000兲.
4. IEEE兾LEOS Annual Meeting Conference Proceedings 共Institute of Electrical and Electronics Engineers, Piscataway, N.J.,
2002兲.
5. F. Tooley, “Optical interconnects do not require improved optoelectronic devices,” in Optics in Computing ’98, P. H. Chavel,
D. A. Miller, and H. Thienpont, eds., Proc. SPIE 3490, 14 –17
共1998兲.
6. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728 –749 共2000兲.
7. K. Iga, M. Oikawa, S. Misawa, J. Banno, and Y. Kokubun,
“Stacked planar optics: an application of the planar microlens,” Appl. Opt. 21, 3456 –3460 共1982兲.
8. M. C. Wu, “Micromachining for optical and optoelectronic systems,” Proc. IEEE 85, 1833–1856 共1997兲.
9. J. Jahns and A. Huang, “Planar integration of free-space optical components,” Appl. Opt. 28, 1602–1605 共1989兲.
10. J. Jahns, “Planar packaging of free-space optical interconnections,” Proc. IEEE 82, 1623–1631 共1994兲.
11. S. Sinzinger and J. Jahns, Microoptics 共Wiley, Weinheim, Germany, 1999兲.
12. H.-P. Herzig, ed., Micro-Optics 共Taylor & Francis, London,
1997兲.
13. S. Sinzinger and J. Jahns, “Integrated micro-optical imaging
system with a high interconnection capacity fabricated in planar optics,” Appl. Opt. 36, 4729 – 4735 共1997兲.
14. W. Eckert, V. Arrizon, S. Sinzinger, and J. Jahns, “Compact
planar-integrated optical correlator for spatially incoherent
signals,” Appl. Opt. 39, 759 –765 共2000兲.
15. D. Fey, W. Erhard, M. Gruber, J. Jahns, H. Bartelt, G. Grimm,
L. Hoppe, and S. Sinzinger, “Optical interconnects for neural
and reconfigurable VLSI architectures,” Proc. IEEE 88, 838 –
848 共2000兲.
16. P. Lukowicz, J. Grzyb, R. Barbieri, G. Tröster, S. Fancey, M.
470
APPLIED OPTICS 兾 Vol. 43, No. 2 兾 10 January 2004
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
Gruber, J. Jahns, and W. Tichy, “Opto-electronic multichip
modules: making optical interconnection packaging compatible with electronic assembly technology,” Opt. Mem. Neural
Netw. 11, 239 –244 共2002兲.
C. Gimkiewicz and J. Jahns, “Thermal management of VCSEL
diode arrays in integrated planar free-space optical systems,”
presented at the Microsystem Technologies 98 meeting, Potsdam, Germany, 1–3 December 1998.
M. Gruber, E. ElJoudi, S. Sinzinger, and J. Jahns, “Practical
realization of massively parallel fiber–free-space optical interconnects,” Appl. Opt. 40, 2902–2908 共2001兲.
K.-H. Gulden, S. Eitel, S. Hunziker, D. Vez, C. Gimkiewicz,
M. T. Gale, and M. Moser, “High density VCSEL arrays,” in
2002 IEEE兾LEOS Annual Meeting Conference Proceedings
共Institute of Electrical and Electronics Engineers, Piscataway,
N.J., 2002兲, pp. 129 –130.
K. W. Goossen, J. A. Walker, L. A. D’Asaro, B. Tseng, R.
Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M.
Chirovsky, A. L. Lentine, and D. A. B. Miller, “GaAs MQW
modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360 –362 共1995兲.
A. V. Krishnamoorthy and D. A. B. Miller, “Scaling
optoelectronic–VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–76
共1996兲.
A. V. Krishnamoorthy and K. W. Goossen, “Optoelectronic–
VLSI: photonics integrated with VLSI circuits,” IEEE J. Sel.
Top. Quantum Electron. 4, 899 –912 共1998兲.
C. B. Kuznia, “Flip chip bonded optoelectronic devices on ultrathin silicon-on-sapphire for parallel optical links,” in Optics in
Computing, Vol. 48 of OSA Trends in Optics and Photonics
Series 共Optical Society of America, Washington, D.C., 2001兲,
pp. 134 –136.
P. S. Guilfoyle and D. S. McCallum, “High-speed low-energy
digital optical processors,” Opt. Eng. 35, 3–9 共1996兲.
R. Hecht-Nielsen, Neurocomputing 共Addison-Wesley, Reading,
Mass., 1990兲.
J. W. Goodman, A. R. Diaz, and L. M. Woody, “Fully parallel,
high-speed incoherent optical method for performing discrete
Fourier transforms,” Opt. Lett. 2, 1–3 共1978兲.
A. A. Sawchuk, B. K. Jenkins, C. S. Raghavendra, and A.
Varma, “Optical crossbar networks,” Computer 20共10兲 50 – 60
共1987兲.
K.-H. Brenner and T. Merklein, “Implementation of an optical
crossbar network based on directional switches,” Appl. Opt. 31,
2446 –2451 共1992兲.
C. P. Barrett, P. Blair, G. S. Buller, D. T. Neilson, B. Robertson,
E. C. Smith, M. R. Tagizadeh, and A. C. Walker, “Components
for the implementation of free-space optical crossbars,” Appl.
Opt. 35, 6934 – 6944 共1996兲.
M. Gruber, S. Sinzinger, and J. Jahns, “Planar-integrated optical vector-matrix multiplier,” Appl. Opt. 39, 5367–5373 共2000兲.
For information on the CO-OP program, see the URL http:兾兾
www.bell-labs.com兾project兾oevlsi兾.
M. Testorf and J. Jahns, “Imaging properties of planarintegrated microoptics,” J. Opt. Soc. Am. A 16, 1175–1183
共1999兲.
F. Wyrowski and O. Bryngdahl, “Iterative Fourier-transform
algorithm applied to computer holography,” J. Opt. Soc. Am. A
5, 1058 –1065 共1988兲.
M. Gruber, D. Hagedorn, and W. Eckert, “Precise and simple
optical alignment method for double-sided lithography,” Appl.
Opt. 40, 5052–5055 共2001兲.
For information on the HOLMS, see the URL http:兾兾www.phy.
hw.ac.uk兾phykjs兾OIC兾HOLMS兾general兾home兾home.html.