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SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Outline • Background • Continuity / Leakage Current Tests • Diode Breakdown / Opens Tests • Channel Potential Test • DC Gain Test • Automated DC Test Set • Summary Ball Aerospace & Technologies Corp. 1 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Background: • Problem: How to quickly and accurately qualify scientific grade CCDs prior to integration into complex packages and/or multi-chip focal plane arrays (e.g. HiRISE and NPOESS-OMPS )? • Full functional (a.k.a. EO or AC) characterization of incoming CCD detectors can sometimes only be performed after expensive package assembly steps have been HiRISE Multi-Detector FPA completed – Discovering CCD tolerance issues after complex packaging steps is expensive and can significantly impact development schedules • EO testing alone does not adequately reveal all potential problems – For example, if Yth and/or Vin for one clock phase significantly differs from the other clocks or inadequate tolerance range • Performing thorough DC characterization is an effective way to quickly and accurately qualify CCDs Ball Aerospace & Technologies Corp. 2 of 19 NPOESS-OMPS FPA June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Background: • The DC tests of most interest in detector screening are: – Continuity Yields pin-to-pin resistance, verifies process, checks for gross ESD damage, and verifies detector arrived without damage – Leakage Current Yields static current draw on each gate, checks for subtle ESD damage, and verifies detector arrived without latent damage – Diode Breakdown Verifies process, and confirms adequate operating margins on drain biases (e.g. OD, RD, and ID) – Diode / Opens Checks for open circuits (e.g. bad/missing wirebonds), verifies diode operation, and checks for intra-layer continuity (e.g. poly 1 to poly 1) – Channel Potential Yields threshold potential and inversion voltage for each gate, verifies optimal clock and bias operating points, and confirms tolerance ranges – DC Gain Verifies amplifier operating point and voltage tolerance ranges • A brief introduction to each of these measurements will be presented followed by some examples of the usefulness of measurements Ball Aerospace & Technologies Corp. 3 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Continuity & Leakage Current Tests: A • Continuity Test – Group two sets of pins together and force a small current (e.g. 1 uA) between the two sets V I SMU - A Mode 1 PIN – To protect CCD detector, the voltage compliance (i.e. the maximum voltage allowed to develop across the two sets of pins) is set to a relatively low voltage, for example +15 volts Gate Input (On-Chip) SUB 2 – If the resistance between the sets of pins is high, voltage compliance will be reached and the test will pass. A + V - – If voltage compliance is not reached, the test is failed and the resultant voltage (and resistance) is reported. – All combinations of gate-to-gate and gate-to-substrate continuity measurements should be performed on every CCD (e.g. OG vs. Sub & R1 vs. R2, etc.) SMU - V Mode Continuity Measurement Setup I 1 + V 2 - Continuity Test Equivalent Circuit Ball Aerospace & Technologies Corp. 4 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Continuity & Leakage Current Tests: A + • Leakage Current Test – Group two sets of pins together and force a small voltage (e.g. +15 v) between the two sets V - SMU - V Mode 1 PIN – To protect CCD detector, the current compliance (i.e. the maximum current allowed to flow between the two sets of pins) is set to a relatively low level, for example 1 uA Gate Input (On-Chip) SUB 2 – If current compliance is not reached and the resultant current is below specification, then the test is passed and the resultant current is reported. – If the resistance between the sets of pins is low, current compliance will be reached and the test will fail. A + V - SMU - V Mode Leakage Current Measurement Setup + – All combinations of gate-to-gate and gate-to-substrate leakage current measurements should be performed on every CCD (e.g. OG vs. Sub & R1 vs. R2, etc.) 1 I V - 2 Leakage Current Test Equivalent Circuit Ball Aerospace & Technologies Corp. 5 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays A Diode Breakdown & Diode Opens Tests: + • Diode Breakdown Test – Sweep reverse bias on a diode input vs. substrate from 0 to absolute maximum value specified by CCD vendor V - SMU - V Mode 1 PIN – To protect CCD detector, the current compliance (i.e. the maximum current allowed to flow in the diode) is set to a relatively low level, for example 5 to 10 uA value dependent on area of diode Diode Input (On-Chip) SUB 2 – If current compliance is not reached or it is reached and the corresponding voltage meets specification, then the test passes A + V - – If current compliance is reached and the corresponding voltage does not meet specification, then the test fails – All input diode pins should be tested vs. substrate (e.g. OD, OS, RD, and ID) – As a precaution this test should not be performed on flight candidate CCD detectors Ball Aerospace & Technologies Corp. 6 of 19 SMU - V Mode Diode Breakdown Measurement Setup + 1 I V - 2 Diode Breakdown Test Equivalent Circuit June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays A Diode Breakdown & Diode / Opens Tests: + • Diode / Opens Test – Apply a fixed forward bias voltage (e.g. 2 v) between a diode input and substrate or between two redundant input signals V - SMU - V Mode 1 PIN – To protect CCD detector, the current compliance (i.e. the maximum current allowed to flow in the diode) is set to a relatively low level, for example 10 to 50 uA Diode Input (On-Chip) SUB – If current compliance is reached, then the conduction path has a low impedance and the test passes – If current compliance is not reached, then the impedance path is high and the test fails 2 A + V - SMU - V Mode – This test should be performed on all diode vs. substrate combinations and between all redundant signals (e.g. R01A vs. R01B) Diode / Opens Measurement Setup + 1 V - I 2 Diode / Opens Test Equivalent Circuit Ball Aerospace & Technologies Corp. 7 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Channel Potential Test: Source Gate • Channel Potential (CP) testing yields the threshold potential (Yth) and inversion voltage (Vin) under many, sometimes all, gates on a CCD detector Drain SiO2 – These two parameters are key for establishing clock and bias operating levels and tolerances A' Y • The basic CP measurement requires a gate surrounded by two drains A – One drain is statically biased on (“Source” in figure) – A small current is sourced into the other drain (“Drain” in figure), which electrically “floats” to the potential under the controlling gate Basic channel potential measurement on a MOSFET A' A • Voltage on gate of interest is swept and the “Drain” voltage (i.e. the gate channel potential) is measured Y YTH • Channel potential testing yields the most information on CCDs with 3 or 4 F architectures, but CCDs with 2 F architectures can also yield significant data • Channel Potential (CP) testing can be performed to some extent on almost all CCD detectors VIN – Most CCD vendors monitor CP test structures on wafers but significant differences from actual CCD data can exist Ball Aerospace & Technologies Corp. 8 of 19 0 VGate Typical channel potential curve June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Channel Potential Test: ABD or ID ABD or ID I01 ABG or IG I01 I01 (OFF) ABG or IG (OFF) ... I01 ... • Determining the best measurement path requires complete design information, which vendors are usually willing to provide I0N I0N RG RD OD ODB RDB RGB RGA RDA ODA Measurement Path ID OSA OSB IG R01 R02 R0N (b) SW OG ABD or ID (OFF) ABG or IG I01 ... I0N (OFF) RG RD OD I0N Ball Aerospace & Technologies Corp. RG RD OD Measurement Path OS ID OS ... (c) SWA OGA R0N I01 I01 ID • Since access to the internal circuitry is quite limited in CMOS based detectors CP measurements are generally not possible R01 R02 ABD or ID ABG or IG I01 OGB SWB Measurement Path (a) ... ... • Split readout serial registers (see (b)), single readout serial registers with electrical injection (see (c)), and parallel registers with electrical injection are ideal architectures for CP measurements on CCD OS ... IG R01 R02 R0N ... SW OG (d) IG (OFF) R01 R02 R0N SW OG Common measurement paths for channel potential testing 9 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays VON + - Channel Potential Test: • All gates in between the measurement drains, other than the gate being measured, must be turned “on” so they don’t influence results I2 I3 + - I1 SWA RGB OGB SWB R1 R2 R3 R1 R2 R3 OGA VSWA RGA RDB RDA ... + - VOFF + - ILOAD VRDB v SS • Other measurement paths must be removed by turning “off” some gates – e.g. If measuring SWA and using two RD drains on either side of the serial register, the parallel register clocks need to be “off” Channel potential setup for Summing Well A (SWA) gate using two amplifier RD drains I01 I01 I03 RGB • Typical measurement current is 20 nA – To high a value can induce a significant I.R voltage drop RGA VOFF + - + - VRDB ILOAD OGB R01 SWB VON Ball Aerospace & Technologies Corp. RDA Measurement Path RDB 10 of 19 + - R02 R03 SWA OGA + VSWA - June 2005, R. Philbrick v SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Channel Potential Test: 0 • Using CP data and design tolerances, complete CP diagrams for the entire CCD can be easily generated • Accurately quantifying changes in Yth as a function of radiation exposure level is needed for space-based applications IG I4 R1 R2 R3 R4 OG 3 3.50 4 3.50 7 7.00 7.40 6.10 5.75 7.40 7.65 7.60 7.60 7.85 9.25 9 10 RD 8.50 7.20 8 RST 5.75 5.90 6 FD Note the significant shift in serial phase 2 (R2) CP from other serial phases 2 Channel Potential • Example here uses +/- 0.1 v design tolerance ID 1 5 SUB = 0V Serial CCD Channel Potential Diagram 8.70 9.45 10.90 11 12 11.10 13 14 15 16.40 16.65 16 16.40 16.90 17.50 17 16.60 16.85 18 18.90 17.10 18.90 16.60 17.70 19.15 19 19.10 20 19.10 19.35 21 22 23 24 ID Ball Aerospace & Technologies Corp. IG I4 R1 R2 11 of 19 R3 R4 OG FD RST RD June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: A A + V - • Test measures the small signal gain of each onchip amplifier by sweeping the reset drain voltage (with reset gate on) and measuring the resultant DC output voltage – Output MOSFET is biased using a constant current load of typically 2 mA SMU - V Mode + VDD CCD Amplifier (On-Chip) RST V - A OUT V SUB SMU - A Mode SMU - V Mode • Small signal gain is calculated using GDC - SMU - V Mode VRD A + V + - dVout VOS dVin VRD Voltage Source DC Gain Measurement Setup • Typical DC gain values range between 0.5 and 0.8 depending on the amplifier configuration (e.g. 1, 2, or 3 stages) + - RD RG • DC gain or equivalent measurements are generally not possible on CMOS based detectors since access to the internal circuitry is limited + - SUB + - OD OS ILOAD v DC gain test equivalent circuit Ball Aerospace & Technologies Corp. 12 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: RD RD OD OD CCD On-chip amplifier CCD On-chip amplifier • Any type of CCD chargeto-voltage amplifier can be measured (e.g. single stage, dual stage, and AC coupled stage) Q1 RG RG Q1 Q2 Q2 Q4 OS D1 D1 OS Q3 Q3 • Optimal operating point and adequate bias tolerances can be quickly verified (both pre and post radiation) SS SS (a) (b) RD OD RD CCD On-chip amplifier I1 OD CCD On-chip amplifier Q1 RG RG • “Bad” MOSFETs can be quickly identified Q1 Q5 Q2 Q2 Q4 Q4 D1 OS D1 Q3 OS Q3 SS (c) LG SS (d) Common CCD Output Amplifier Configurations: (a) Single-Stage Source Follower, (b) Two-Stage Source Follower, (c) Two-Stage Source Follower with Bias Control, and (d) AC Coupled, Two-Stage Source Follower Ball Aerospace & Technologies Corp. 13 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: VOS • Slope of small signal gain curve around operating point gives a measure of the low frequency linearity response GAIN Direction of Increasing Signal VRG-CUT VRG-CUT VRD VRD Output Response and Small Signal Gain for a typical DC coupled amplifier • AC coupled amplifiers yield a slightly different shaped DC gain curve due to the presents of the line reset MOSFET – Two distinct cutoff points are observed • • Vout VOS Vin VRD GAIN • A typical input (RD) versus output (OS) curve is shown at right along with small signal gain GDC Line reset MOSFET cut off point Reset MOSFET cut off point VQ5-OFF – Gate of line reset MOSFET should be held “off” during the entire scan VRG-CUT VRD Example of DC gain curve for AC coupled two stage amplifier Ball Aerospace & Technologies Corp. 14 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Automated DC Test Set: • Basic components of a fully automated DC test set are – A programmable cross point matrix to make/break all required connections – A programmable DC Parameter Analyzer • At least 4 Stimulus/Measurement Units (SMUs) are needed, but having more than 4 enables other DC measurements – Generic DC adapter box (supports automated and manual DC testing) – Personal Computer with GPIB (IEEE-488) interface – Single DC adapter board per detector Computer Matrix HP4141 DC Adapter Box Automated DC test set at Ball Aerospace & Technologies Corp • All DC measurements described here can also be performed manually using accurate current / voltage sources and meters – Very time consuming! Ball Aerospace & Technologies Corp. Each detector requires only a simple DC adapter board, all other hardware is common 15 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Automated DC Test Set: • All test equipment is controlled through a single, simple program – User friendly GUI allows wide range of user (operator engineers) – Priority access prevents operators from making changes to critical parameters • All test results and conditions are stored automatically after each test • Interactive measurements possible using HP4141 virtual instrument interface • Test results easily imported to other analysis programs (e.g. Excel, IDL) Automated DC test set interface software – Channel potential test example shown Ball Aerospace & Technologies Corp. 16 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Summary: Preferred Operating Point Vendor Recommended Operating Point ESD damage occurring during packaging/shipping Processing problems (e.g. low diode breakdowns) Non-optimal amplifier operating point Non-optimal bias levels (e.g. OG, RD or OD) Inadequate bias tolerances • To account for variability in electronics design, within CCD population, or resulting from post radiation shifts VRD Example of bad recommended DC operating point Y Preferred Operating Point Non-Optimal OD Operating Point GAIN – – – – – GAIN • Some examples of problems identified during DC testing YTH Vendor Recommended Operating Point Phase 1 Phase 2 VINV Range VRG-CUT 0 Range VRD VGate Example of bad recommended OD bias point Example of gate to gate channel potential variability Ball Aerospace & Technologies Corp. 17 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Summary: • DC characterization provides a fast, accurate, and thorough means for evaluating incoming CCD detectors • Thorough DC characterization does not replace full AC characterization but does significantly speed the process of AC characterization and FPA build up – It allows the build up of complex and expensive multidetector FPAs to proceed with high confidence that all CCDs are “healthy” and have necessary clock and bias tolerances • Thorough DC characterization on CCDs early on in a program can identify processing and design problems – Most CCD vendors do not perform such exhaustive DC testing on CCDs (wafer level or packaged) due to time/cost – DC testing during pre/post radiation studies is recommend • Thorough DC and AC characterization enables fixed voltage systems to be employed in space-based applications with high confidence • DC characterization provides vital information for pre/post radiation testing (e.g. see examples ) Ball Aerospace & Technologies Corp. DC data from pre/post radiation and vac-bake experiments 18 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Summary: • Complete DC testing is performed on all incoming CCDs at Ball, often multiple times during assembly of a FPA • Recommended order for performing DC tests is shown in tables at right • A subset of the DC tests presented can also be performed on CMOS based detectors – Due to intervening circuitry, however, it is usually not possible to perform the channel potential and DC gain tests Recommended Order for DC Testing CCD Order 1 2 3 4 5 6 • Questions? DC Test Continuity Test Leakage Current Test Diode Breakdown Test* Diode Opens Test Channel Potentials Test DC Gain Test CMOS – Contact information: Rob Philbrick Ball Aerospace & Technologies Corp. P.O. Box 1062, Mail Stop: CO-5 Boulder, CO 80306 (303) 939-5399 [email protected] Ball Aerospace & Technologies Corp. 19 of 19 Order 1 2 3 4 DC Test Continuity Test Leakage Current Test Diode Breakdown Test* Diode Opens Test * As a precaution, the diode breakdown testing should not be performed on flight candidate detectors June 2005, R. Philbrick