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SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Outline • Background • Channel Potential Test • DC Gain Test • Summary R. Philbrick & M. Blouke Ball Aerospace & Technologies Corp. Ball Aerospace & Technologies Corp. 1 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Background: • Problem: How to quickly and accurately qualify scientific grade CCDs prior to integration into complex packages and/or multi-chip focal plane arrays (e.g. HiRISE and NPOESS-OMPS )? • Full functional (a.k.a. EO or AC) characterization of incoming CCD detectors can sometimes only be performed after expensive package assembly steps have been HiRISE Multi-Detector FPA completed – Discovering CCD tolerance issues after complex packaging steps is expensive and can significantly impact development schedules • EO testing alone does not adequately reveal all potential problems – For example, if Yth and/or Vin for one clock phase significantly differs from the other clocks or inadequate tolerance range • Performing thorough DC characterization is an effective way to quickly and accurately qualify CCDs Ball Aerospace & Technologies Corp. 2 of 19 NPOESS-OMPS FPA June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Background: • The DC tests of most interest in detector screening are: – Continuity Yields pin-to-pin resistance, verifies process, checks for gross ESD damage, and verifies detector arrived without damage – Leakage Current Yields static current draw on each gate, checks for subtle ESD damage, and verifies detector arrived without latent damage – Diode Breakdown Verifies process, and confirms adequate operating margins on drain biases (e.g. OD, RD, and ID) – Diode / Opens Checks for open circuits (e.g. bad/missing wirebonds), verifies diode operation, and checks for intra-layer continuity (e.g. poly 1 to poly 1) – Channel Potential Yields threshold potential and inversion voltage for each gate, verifies optimal clock and bias operating points, and confirms tolerance ranges – DC Gain Verifies amplifier operating point and voltage tolerance ranges Ball Aerospace & Technologies Corp. 3 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Channel Potential Test: Source Gate • Channel Potential (CP) testing yields the threshold potential (Yth) and inversion voltage (Vin) under many, sometimes all, gates on a CCD detector Drain SiO2 – These two parameters are key for establishing clock and bias operating levels and tolerances A' Y • The basic CP measurement requires a gate surrounded by two drains A – One drain is statically biased on (“Source” in figure) – A small current is sourced into the other drain (“Drain” in figure), which electrically “floats” to the potential under the controlling gate Basic channel potential measurement on a MOSFET A' A • Voltage on gate of interest is swept and the “Drain” voltage (i.e. the gate channel potential) is measured Y YTH • Channel potential testing yields the most information on CCDs with 3 or 4 F architectures, but CCDs with 2 F architectures can also yield significant data • Channel Potential (CP) testing can be performed to some extent on almost all CCD detectors VIN – Most CCD vendors monitor CP test structures on wafers but significant differences from actual CCD data can exist Ball Aerospace & Technologies Corp. 4 of 19 0 VGate Typical channel potential curve June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays VON + - Channel Potential Test: • All gates in between the measurement drains, other than the gate being measured, must be turned “on” so they don’t influence results I2 I3 + - I1 SWA RGB OGB SWB R1 R2 R3 R1 R2 R3 OGA VSWA RGA RDB RDA ... + - VOFF + - ILOAD VRDB v SS • Other measurement paths must be removed by turning “off” some gates – e.g. If measuring SWA and using two RD drains on either side of the serial register, the parallel register clocks need to be “off” Channel potential setup for Summing Well A (SWA) gate using two amplifier RD drains I01 I01 I03 RGB • Typical measurement current is 20 nA – To high a value can induce a significant I.R voltage drop RGA VOFF + - + - VRDB ILOAD OGB R01 SWB VON Ball Aerospace & Technologies Corp. RDA Measurement Path RDB 5 of 19 + - R02 R03 SWA OGA + VSWA - June 2005, R. Philbrick v SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Channel Potential Test: 0 • Using CP data and design tolerances, complete CP diagrams for the entire CCD can be easily generated • Accurately quantifying changes in Yth as a function of radiation exposure level is needed for space-based applications IG I4 R1 R2 R3 R4 OG 3 3.50 4 3.50 7 7.00 7.40 6.10 5.75 7.40 7.65 7.60 7.60 7.85 9.25 9 10 RD 8.50 7.20 8 RST 5.75 5.90 6 FD Note the significant shift in serial phase 2 (R2) CP from other serial phases 2 Channel Potential • Example here uses +/- 0.1 v design tolerance ID 1 5 SUB = 0V Serial CCD Channel Potential Diagram 8.70 9.45 10.90 11 12 11.10 13 14 15 16.40 16.65 16 16.40 16.90 17.50 17 16.60 16.85 18 18.90 17.10 18.90 16.60 17.70 19.15 19 19.10 20 19.10 19.35 21 22 23 24 ID Ball Aerospace & Technologies Corp. IG I4 R1 R2 6 of 19 R3 R4 OG FD RST RD June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: A A + V - • Test measures the small signal gain of each onchip amplifier by sweeping the reset drain voltage (with reset gate on) and measuring the resultant DC output voltage – Output MOSFET is biased using a constant current load of typically 2 mA SMU - V Mode + VDD CCD Amplifier (On-Chip) RST V - A OUT V SUB SMU - A Mode SMU - V Mode • Small signal gain is calculated using GDC - SMU - V Mode VRD A + V + - dVout VOS dVin VRD Voltage Source DC Gain Measurement Setup • Typical DC gain values range between 0.5 and 0.8 depending on the amplifier configuration (e.g. 1, 2, or 3 stages) + - RD RG • DC gain or equivalent measurements are generally not possible on CMOS based detectors since access to the internal circuitry is limited + - SUB + - OD OS ILOAD v DC gain test equivalent circuit Ball Aerospace & Technologies Corp. 7 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: RD RD OD OD CCD On-chip amplifier CCD On-chip amplifier • Any type of CCD chargeto-voltage amplifier can be measured (e.g. single stage, dual stage, and AC coupled stage) Q1 RG RG Q1 Q2 Q2 Q4 OS D1 D1 OS Q3 Q3 • Optimal operating point and adequate bias tolerances can be quickly verified (both pre and post radiation) SS SS (a) (b) RD OD RD CCD On-chip amplifier I1 OD CCD On-chip amplifier Q1 RG RG • “Bad” MOSFETs can be quickly identified Q1 Q5 Q2 Q2 Q4 Q4 D1 OS D1 Q3 OS Q3 SS (c) LG SS (d) Common CCD Output Amplifier Configurations: (a) Single-Stage Source Follower, (b) Two-Stage Source Follower, (c) Two-Stage Source Follower with Bias Control, and (d) AC Coupled, Two-Stage Source Follower Ball Aerospace & Technologies Corp. 8 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays DC Gain Test: VOS • Slope of small signal gain curve around operating point gives a measure of the low frequency linearity response GAIN Direction of Increasing Signal VRG-CUT VRG-CUT VRD VRD Output Response and Small Signal Gain for a typical DC coupled amplifier • AC coupled amplifiers yield a slightly different shaped DC gain curve due to the presents of the line reset MOSFET – Two distinct cutoff points are observed • • Vout VOS Vin VRD GAIN • A typical input (RD) versus output (OS) curve is shown at right along with small signal gain GDC Line reset MOSFET cut off point Reset MOSFET cut off point VQ5-OFF – Gate of line reset MOSFET should be held “off” during the entire scan VRG-CUT VRD Example of DC gain curve for AC coupled two stage amplifier Ball Aerospace & Technologies Corp. 9 of 19 June 2005, R. Philbrick SDW 2005 DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays Summary: Preferred Operating Point Vendor Recommended Operating Point ESD damage occurring during packaging/shipping Processing problems (e.g. low diode breakdowns) Non-optimal amplifier operating point Non-optimal bias levels (e.g. OG, RD or OD) Inadequate bias tolerances • To account for variability in electronics design, within CCD population, or resulting from post radiation shifts VRD Example of bad recommended DC operating point Y Preferred Operating Point Non-Optimal OD Operating Point GAIN – – – – – GAIN • Some examples of problems identified during DC testing YTH Vendor Recommended Operating Point Phase 1 Phase 2 VINV Range VRG-CUT 0 Range VRD VGate Example of bad recommended OD bias point Example of gate to gate channel potential variability Ball Aerospace & Technologies Corp. 10 of 19 June 2005, R. Philbrick