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EE 466: VLSI Design
Lecture 03
Channel Length Modulation
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The inversion layer charge QI
represents the total mobile electron
charge on the surface and its
expression at the source end of the
channel is:
QI at x=0=-Cox(VGS-VT0) and the
inversion layer charge at the drain end
of the channel is expressed as: QI at
x=L=-Cox(VGS-VT0-VDS)
At the edge of saturation when the
drain-to-source voltage reaches
saturation (VDS=VDSAT=VGS-VT0) the
inversion layer charge at the drain end
becomes zero.
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We can approximate the inversion
layer charge at the drain end by QI at
x=L=0 (even though this is not quite
true)
When VDS=VDSAT, the channel is
pinched off at the drain end.
Further increase of the drain-tosource voltage (VDS>VDSAT) results in
even a larger pinched-off portion of
the channel.
The effective channel length is
reduced to: L’=L-DL where DL is the
length of the channel where QI=0.
The pinch-off point moves from the
drain end of the channel towards the
source end with increasing VDS.
Channel Length Modulation
• For L’<x<L the channel voltage is
Vc at x=L’=VDSAT.
• The electrons traveling from
source to drain traverse the
inverted channel segment of
length L’ and then they are
injected into the depletion region
of length DL that separates the
pinch-off point from the drain
edge.
• The gradual channel
approximation is valid in this
region and is given by:
IDSAT=(mnCox)/2(W/L’)[VGS-VT0]2
• The effective channel length for
the MOSFET operating in
saturation is now L’ and the above
equation accounts for the actual
shortening of the channel.
• Shortening of the channel is also
known as channel length
modulation.
• If L’ is replaced by L in the
equation we can show that the
computed saturation current using
L’ is greater than the new IDSAT
computed using L.
Channel Length Modulation
• We must modify the equation for
saturation current so that it
reflects the dependency on VDS.
Note that the saturation current
will increase with increasing VDS
since L’ decreases with increasing
VDS.
I DSAT


 1 m C W
 n ox VGS  VT 0 2

 1  DL  2 L
L 

• The first term of the equation
accounts for the channel length
modulation effect.
DL 
VDS  VDSAT
• Let 1-DL1-lVDS, with l being
an empirical model parameter
called the channel length
modulation coefficient.
• Assume that lVDS<<1 then the
saturation current becomes:
I DSAT 
mnCox W
2
L
VGS  VT 0 2 1  lVDS 
• The above equation can be used
with sufficient confidence for
most first order hand calculations
The Threshold Voltage
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Any gate-to-source voltage less than
VT0 is not sufficient to establish an
inversion layer.
The MOSFET conducts no current
between its source and drain terminals
unless VGS is greater than VT0.
Oxide (SiO2)
Metal (Al)
P-type Semiconductor (Si)
Ec
2FF
qVT0
FF
FF
Ei
EFp
Ev
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Increasing the gate-to-source voltage
above and beyond VT0 will not affect
the surface potential and the depletion
region depth.
There are 4 physical properties that
affect the threshold voltage namely (i)
the work function difference between
the gate and the channel, (ii) the gate
voltage component to change the
surface potential, (iii) the gate voltage
component to offset the depletion
region charge and (iv) the voltage
component to offset the fixed charges
in the gate oxide and in the silicon
oxide interface.
The Threshold Voltage
• The work function difference
(Fgate-to-channel) reflects the built in
potential of the MOS structure
which consists of the p-type
substrate, the thin silicon dioxide
layer and the gate electrode.
• FGC = FF(substrate) –FM if the
gate material is metal (Aluminum)
• If polysilicon is the gate material:
FGC = FF(substrate) – FF (gate)
• An externally applied voltage
must be changed to achieve
surface inversion i.e. to change
the surface potential by -2FF.
• The depletion region charge
density at surface inversion (FS =
-FF) is QB0=-(2qNASi|-2FF|)-1/2
• Assuming that the substrate is
biased at a different voltage level
than the source (at ground) then
the depletion region charge
density can be expressed as a
function of the source-to-body
voltage VSB: QB=-(2qNASi|-2FF|+
VSB)-1/2
• The third component offsets the
depletion region charge and is
equal to –QB/Cox (Cox=ox/tox).
The Threshold Voltage
• The gate voltage that is necessary
to offset to the fixed positive
charge density Qox (at the
interface between the gate oxide
and the silicon substrate) is
–Qox/Cox.
• Combining all the voltage
components we can determine the
threshold voltage. For zero
substrate bias VT0 is given by:
VT0=FGC-2FF-QB0/Cox-Qox/Cox
• Thus determine the expression for
nonzero substrate bias.
Body effect
• The most general form of the
threshold voltage is: VT=FGC2FF-Qox/Cox-QB/Cox
VT  VT 0   

 2F F  VSB  2F F
• VT=VT0-(QB-QB0)/Cox
• (QB-QB0)/Cox=((2qNASi)-1/2)
/Cox*((|-2FF+VSB|)-1/2-(|2FF|)-1/2)
• This becomes the most
general expression of the
threshold voltage with the
parameter gamma being:

2qN A Si
Cox

The Threshold Voltage
• Gamma is called the substratebias or the body effect coefficient.
• The general expression for the
threshold voltage can be used for
both the n-channel and p-channel
devices.
• The differences are as follows:
– Substrate Fermi potential FF is
negative in nMOS but positive
for pMOS.
– The depletion region charge
densities QB0 and QB are negative
for nMOS but positive for pMOS
• Further differences:
– The substrate bias coefficient  is
positive for nMOS and negative
for pMOS.
– The substrate bias voltage VSB is
positive in nMOS but negative
for pMOS.
• Typically the threshold voltage of
an enhancement mode n-type
MOSFET is a positive quantity
while that of a p-type MOSFET is
negative.
Sub-Threshold Conduction
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Ideally at VGS < VT, ID = 0.
The MOS device is partially
conducting for gate voltages below
the threshold voltage.
This is termed sub-threshold or weak
inversion conduction.
In most digital applications the
presence of sub-threshold current is
undesirable. Why?
….most digital applications …. Does
this mean some digital applications
can tolerate sub-threshold currents?
A Sub-threshold digital circuit
manages to satisfy the ultra-low
power requirement. How?
•
What type of digital applications can
benefit from this ultra low power
design approach?
Subthreshold Conduction
• Below cut off current does not abruptly
become zero
Vgs Vt
I ds  I ds0 e
• Falls off exponentially
nvT
(1  e

Vds
vT
)
I ds0  v e
2 1.8
T
• Useful in low power CMOS VLSI design
Junction Leakage
• Conduction even
when transistor is in
cut-off
• Substrate to diffusion
junctions are reverse
biased
• However reverse
biased diodes do
conduct leakage
current
I D  I S (e
VD
vT
 1)
Leakge Current
• When the junction bias voltage is
significantly more than the thermal voltage
(~26mV @room temperature) the leakage
current is –Is
• Junction leakage limits storage time in onchip memory elements
– Requires refreshing dynamic nodes
Tunneling effects
• Ideal MOS model
– High input impedence
– No static current flow through the gate terminal
• Quantum mechanical effect
– Carriers “tunnel” through insulating barriers with finite
probability
– Insulating barrier has to be very thin for appreciable
current
• Current gate oxide thickness ~10-15Å
– Single atomic layer of silicon ~3Å
Tunneling current
• Current technology nodes
– Tunneling current as significant as junction leakage
and sub-threshold conduction
• Technique to reduce tunneling current
– Use high-K materials in the gate oxide layer
• High dielectric constant makes high gate
capacitance
– Reduces the need to reduce the oxide thickness
– Silicon Nitride is a good candidate for such materials
Temperature Effects
• Effect on Mobility
• Carrier mobility
decreases with
temperature
• kµ is a parameter
usually in the range
1.2-2.0
T
m (T )  m (Tr )
 Tr



km
Temperature effects
• Threshold voltage
– Vt decreases linearly with increase in
temperature
• Junction leakage also increases with
increase in temperature
• All combined results in decrease of On
current and increase of Off current
Temperature Issues
• Circuit performance is therefore generally worse at high
temperatures
• Conversely cooling can enable better performance
• Cooling techniques
– Convection
• Natural
• Fans
• Heat sinks
– Active cooling
• Water cooling
• Liquid nitrogen
• Cost of methods have to be justified
Non-Ideal I-V Effects (Summary)
• Miniaturization has led to modern
devices having nonideal
characteristics
• The saturation current increases
less than quadratically with
increasing VGS.
• Velocity saturation and mobility
degradation are two of the effects
that cause the non quadratic
current increase with VGS.
• When carrier velocity ceases to
increase linearly with field
strength we have velocity
saturation.
• The current IDS is lower than
expected at high VDS.
• There are several sources of
leakage that result in current flow
when the transistor is expected to
be OFF.
• The source and drain diffusion
regions are form reverse biased
diodes which experience junction
leakage into the substrate or well.
• The current into the gate IG is
ideal zero, however as gate oxide
thickness is reduced electrons
tunnel through the gate, causing
some current.