Download Current Simulation for CMOS Circuits

CARNEGIE
MELLON
Current Simulation
for CMOS Circuits
Greg
Blum
1992
Current Simulation for CMOS
Circuits
Greg Blum, Advisors: Prof Wojciech Maly and Prof. Ronald Rohrer
1.0 Introduction:
A growing concern in VLSI design is the reliability of fabricated CMOS
integrated circuits. Two
important issues that determine the reliability of an integated circuit are electromigration and IRnoise. Electromigration causes failures to occur by excessive electron flow which can create an
open or short circuit on or between metal lines. The failure rate is determined by the current density that is flowing through a cross section of a metal line. As a result of electromigration, a hard
failure can and usually will occur. On the other hand, IR-noise causes failures to occur by inducing a false state within a circuit. This failure is transient in nature and can be avoided by reduced
transition times or by re-transmitting the data. Neither of these options, however, is attractive to
employ.
To determine the effect of both electromigration and IR-noise, current flow information on the circuit’s power lines is needed. The power lines are usually the critical factor for determining the
affects of electromigration or 1-R-noise because the greatest currents can be found flowing through
these lines. In both cases, the transition that causes the largest amountof current to flow through
the power lines must be found to determine the worst case conditions on the line. The current
waveformwith the greatest peak value is needed to determine the effect of IR-noise. For electromigration, the current waveformthat dissipates the most energ~y is needed. Unfortunately, the difficulty involved in obtaining these currents is a function of the numberof inputs to the circuit. It is
impractical to fully analyze a circuit to determine its worst case time average and peak currents
since there are a possible 22n transitions for an n input circuit. Onthe other hand, it has been
shown that to find ~he proper excitation needed for the peak power is an NP-complete problem[5].
Therefore a methodthat can find the transition or a small sub-set of transitions that causes the
worst currents to flow must be developed.
One method has been developed to avoid the problem of finding the needed transition. The
CRESTsimulator described in [1] and [6] uses probabilistic simulation to find the expected current waveform. The expected current waveformis the meancurrent that would result if all inputs
were considered over time. Although these probabilistic waveforms may be a representative sample of the expected output waveforms, there is no guarantee that the probabilistic waveformwill
have any direct correlation to the desired worst case waveforms. Therefore, new methods must be
developed that will limit the numberof input transitions that must be tested to detemaine circuit
reliability.
After the proper input transitions are determined and the currents are calculated, a question still
remains as to how to interpret the derived information. It has been proposed in [8] that the power
lhae networks can be broken into subnetworks. These small subnetworks could then be approximated in temas of current sources. The current sources from each of these subnerworks would
then be combined to~ether with resistors, capacitors, and inductors. The current found in each
branch and the voltage on each node could then be demrmined. The results could then be cornCurrem Simulation
for
C.MOS Circuits
1
pared to assure that the current density on each line and the voltages at each node did not exceed
an accepted value. Using this simplified model, the stress caused by IR-noise and electromigration
on the total network may be determined as well.
The objective for this paper is to show that the current found on the power lines can be determined
efficiently given a set of input transitions. The emphasis is on fully complementary CMOS,but
the method is general enough to be applied to most CMOS
technology. Currently, there are many
simulators which have been developed that will determine the current waveforms on power lines.
However, these simulators are typically general purpose simulators which are mainly used to find
voltage waveforms. Therefore, even for moderately sized circuits, they tend to take an excessive
amount of time to run. To decrease the amount of simulation time needed, a current timing simulator will be developed. The approach taken is similar to the methoddescribed in [2] except that it
eliminates the need for table look-up and does not assume a symmetric triangular current waveform. Our approach will use a simplified MOSFET
transistor model to promote an increase in
speed that will compensate for any loss in accuracy that mayoccur during simulation.
This paper will be partitioned in the following manner. First, symbol conventions that will be used
throughout the paper will be introduced. Next, the current waveformapproximation will be established using a simplified transistor model. Then the validity of the approximation will be discussed. A general transistor model will then be presented. Finally, somecircuit results will be
presented along with some conclusions.
2.0 Terminology:
Throughout this paper the following symbol conventions will be used:
0 meansheld at state zero,
1 meansheld at state one,
^0 meansa transition from state one to state zero,
^1 meansa transition from state zero to state one.
3.0 Approximating Gate Current:
In general, a complex CMOS
circuit can be partitioned into simplified subnetworks called gates.
A gate is constructed by joimng transistors together to form a given logic function. A gate can
have manyinputs, but only one output. The current on a gate’s power and ground lines is a function of all the inputs, the output, and the characteristics of the transistors that comprise the gate.
However,it would be beneficial if the current on the gate’s power lines could be simplified so that
the total current of the circuit could be quic "tdy and efficiently determined without solving for the
current at manydiscrete time points.
The power/groundcurrent through a gate is approximately triangular with respect to tinge. That is
the current will start at an initial value, rise linearly for an mnountof time, and then linearly
decrease back to its initkd value. For fully complementaryCMOS
gates, the initial starting value
is zero. Since ~he initial value is zero, ~o uniquely determine a given tri;m~]e three time points
Currcnl Simulation
for CMOSCircuiL~
one maximumheight are needed. Using a triangle approximation, it seems plausible that the current can be calculated efficiently because there are only a few number of time points needed.
The simplest gate, the inverter, will be studied first to demonstrate the plausibility of using a triangular approximation for the current. Initially, a simplified model will be used for ease in presentation of the method. The method will then be extended to general CMOSgates, and then some
restrictions that had been placed upon the input voltage waveform wilt be removed.
3.1 Transistor Equations
In general CMOS
transistors
ID =
can be characterized by the following set of equations:
~[2(VGs-VT)VDs-VDs2](1+ )~VDs) VGS>=
I D = ~(VGs-VT)2(1
+ )~VDs)
VT &
T VDS < VGs-V
VGS >= VT &
T VDS >= VGs-V
ID= 0
VGS
< V
T
(Linear)
0EQ1)
(Saturation)
0EQ2)
(Cutoff)
(EQ3)
where VGSis the gate to source voltage, VDS is the drain to source voltage, VT is the threshold
voltage, 9~ is the channel length modulation factor, and ~3 is the transconductance. Whenmaking
calculations with these equations, the absolute value of all voltages should be used. Implemented
in this way, they can be used for both NMOS
and PMOSdevices as long as the correct current
direction is employedfor each tYtX~of device.
3.2 The Inverter
Using the transistor modelof Fig-ure 1, the load found on the output of an inverter (see Figx~re 2)
the lumped sum of capacitors from the output node to power and ground. These capacitors are the
sum of parasitic capacitors due to loading of the next stages along with the capacitance associated
with the metal interconnection between gates. As a first approximation, the current that flows
from Via to power and g-round is ignored. This assumption is valid as long as all the capacitors
found on the positive node of the voltage source are to ~ound and the negative node of the volt-
vdd
V
d
C
n
Vg
V
S
Ignd
FIGURE 1.
The Simplified
"lransislor
--~t S~rnulat~c n for CMOS
Circuiks
M~del
l" I1,1,~. R t. _. A Typical Inverter
age source is to ground. Then the input vohage source to has a localized loop of current which
will not affect the overall current supplied by the power sources.
To determine the amount of current that is suppIied by the power sources, the sum of the individual branch currents must be found. A branch can be either a transistor or capacitor in this case.
From KCLthe power and ground currents are:
Ignd= In + Ion
(EQ4)
Ivdd= -(Ip +Icp).
(EQ 5)
The power source current will always be the negative of the ground source current. Since current
through the transistors generally flows toward the ga-ound source, the ground source current will
generally be positive and therefore the ground source current will be considered for the duration
of this paper. A typical g-round current plot caused by an inverter with a moderateload is sho~a~nin
Figure 3. Whata moderate load is will be determined later in Section 4.0. Observe that the
inverter current plot of Fi~oaare 3 is approximatelytriang-ular. Therefore, as stated earlier, a triang-ular approximation should suffice.
Assumethat there is no static short circuit current. Only the NvMOS
or PMOStransistor conducts
at any given time. Therefore, only the current of the conducting transistor needs to be analyzed. In
general, static short circuit currents are Iess than 20%of the total current [3]. Hence to assume
that there is no short circuit current is typically a reasonable first order approximation. In CMOS
circuits, current only flows whenthere is a state transition on one or more of the gate inputs.
Therefore, the inverter needs only be analyzed beginning whenits input initially changes state
until the transient currents settle back to their steady state values.
Under these simplifying assumptions and using simple current division,
Ip(~pCn+ In~3nC-~P
Ignd -- Ctot
Ctot
0EQ6)
where Ctot equals C.n + Cp and ~p equals 1- ~,n- Since only one transistor conducts at a time, ~n
equals 1 if Vin makesa ^ 1 transition and ~n equals 0 if Vin makesa ^0 transition. Therefore, the
Time (ns)
FIGIJRt£3. Typicalt;NI) Current t’~r an lnve,’ler
Current
Simulalion
h,r CMOSCircuils
4
input transition determines which transistor
when Vin makes a ^1 transition:
Ignd-
is to be analyzed at a given time. Consider the case
InCp
Ctot
(’EQ7)
Using the general CMOS
equations, I n equals zero until Vin equals Vm, since Vgs equals Vin. If
Vin is assumedto vary linearly with respect to time with slope c~, the delay time, Td, equals
Note that this is not the usual definition for the delay time, but it adequate and will be used
throughout this paper. Morespecifically, the delay time is defined to be the time at whicha driving
transistor starts to conduct. Since Vout equals Vdd whenVin initially becomesgreater than Vtn, the
NMOS
transistor is in saturation. At this time,
OEQ8)
Using the initial
condition that Vout equals Vdd and solving the differential
~n~.
(Vin
equation,
_ "Vtn)
3t (ZCto
where Vin equals o:t. Since this equation is only valid as long as Vout >= Vin - Vm,the condition
Vout equals Vin t Vtn can be solved to determine the point at which the transistor reaches the end
of saturation. Using the three highest order terms of the Taylor series expansion of the ln(l+x), the
resulting cubic equation can be solved to determine values for Vout, Vimand T1. T1 is the time at
which Vout equals Vin - Vtn. The current at this time, I 1, can be found by solving the linear characteristic equation with the derived input and output voltages. It should be noted that similar equations can be found for the case whenVin makes a ^0 transition.
Recall that the ground current waveformof the inverter is to be approximated by a waveformthat
is triang-ular. The area under such a triangle is Ii*(At)/2 where At equals T2-Td (see Figure 4). The
area is also equal to the total amountof charge, Q. For a gate that changes state from one power
rail to the other, Q is C.totXZdd which is the amountthat must be charged or discharged through the
transistors in the gate. If it is assumedthat the peak value, I1, occurs at T1, then the time T2, at
which 12 goes back to zero, can be calculated. Specifically,
2CtotVdd
T2 = Td + I1
(EQ 10)
Using this procedure, I n is determined and Ignd is plotted to be comparedwith the results obtained
using HSPICEwith BSLMmodels (see Figure 5).
The triangle approximation thus far is able to approximate most of the curve. It has the correct
delay time, and it follows the general rising and falling slopes of the curve. However,the triangle
does not take up as nmcharea as the real gate current cu1-,’e. This enor was expected because of
t}?e assumptionfi~aI Iherc is i~o shoi~ circuit curre1~t. To compcnsalefor the short circuit current,
Currcn~ Simulation
for CMOSCircuits
5
ID
50.00
.....
100.00
.....
50.00
......
0.00
0.00
2.00
4.00
Time
Time (ns)
.FIGURE,5.GroundCurrentand Triangle Approximation.
FIGURE
4. A General Triangle
somearea must be added to the triangle. Since the slopes of the triangle are correct, a similar triangle can be formed that includes the remaining desired area. To form a similar triangle, an area A
is added to the original triangle that has the same slopes as the original triangle (see Figure 6).
Since a new area is being added, the new height, 12, and the difference in time, At1 must be found.
Therefore, the reIationships between A, 12, and Atl, must be calculated.
Since the leading edge of the triangle is linearly rising, the time at which12 occurs is
"12 = ~;(TI’-Td)
(’EQ11)
By construction, the area is given by:
A = I1At ~ +
(I 2 - Ia) At1 (I 2 + I 1) At
1
2
=
2
(EQ12)
At
1
T1
1’ T
Time
T2
1T2’At
FIGURE
6. Triangle u~lh Area Added
Current Sunulation for CMOS
Circuits
6
Similarly, by construction, At1 can be computedto be:
At 1 -
12 - I 1 12I~ (~ + C~
+ 2)
52
51
2515
(I2 -- I1)
(EQ13)
where ~x1 = I1/(T1-Td) and 2 = I1/(T2-T1). Combining the two pr evious eq uations yi elds:
(0:1 + ct2) (I22.- I12)
(EQ14)
Rearranging and solving for I2:
(EQ 15)
IrA is given, 12 can be obtained using Equation I5, and that result along with Equation 13 can be
used to find ZXt1. Nowthat the relationships have been established between I2, At1, and A, the area
to be added to the original triangle still remains to be calculated.
Since short circuit current is primarily a DCphenomenon,a DCsolution to the area will be
sought. To find the DCcurrent of an inverter, the drain currents of the PMOSand NMOS
transistors are set equal to each other and all of the capacitors are opened. Whenthe current is plotted
versus the input voltage (see [7]), the maximum
current occurs whenthe input voltage is equal
the output voltage. Therefore, both transistors are in their saturation modesof operation. Hence,
the maximumcurrent caused by the input, Vm,is:
Vm =
0EQ16)
l+x
where x2 = ~/~n-Since it was assumed that the input was linear in time, the time, Tm, at which
this occurs is:
Tm -
Vm
(EQ17)
whereoc is the slope of the input.
Returning to the inverter, it was originally assumedthatthe PMOS
transistor was cutoff whenVin
equaled ^1. However,according to the fundamental transistor equations, the PMOS
transistor will
be in its linear modeof operation whenthe NMOS
transistor starts conducting, since Vout equals
Vdd. For now, let it be assumed that the maximum
short circuit current also occurs while the
PMOStransistor remains in its linear region. This maximumcurrent would then be given by
Equation 1, using the appropriate PMOS
parameters. FromEquation 1, to determine this short circuit current, Ipm, values for the input voltage and the out-put voltage are required. In [3], it was
observed that the maximum
current occurs at a time equal to or greater than the time predicted
Current Simulation
for CMOSCircuits
7
from the DCsolution. Since this is the case, let it be assumedthat Ipmoccurs at time Tpmwhich is
defined to equal Tm + Td. The input, Vin(Tpm), then equals o:Tpm. To find the output voltage,
Vout(Tpm),the original triangle approximation without the short circuit current is used. Since it
was originally assumed that the PMOSdevice was not conducting, Vout is given by
~ In
Vout
(t)
---~
T
d
~ ~---~t
vtot
+ Vout
(EQ 18)
(Td)"
Solving this equation for the different regions of operation given the original triangle approximation:
while Td < Thn <= T~,
Vvout = Vdd--
2Cto
I1 t
(T1 ++Td
Ta)2 )+ CtotI1TaTpm
(T 1 + Ta) ;
(T~m
(EQ 19)
while T1 < Tprn 2,
<T
Vpout
= Vdd --
2Cto
II(TI+Td)
t
II(Tpm+T
2Ctot (T2 )+. T1
~) + I~(Tpm-T~)2
0EQ20)
Ctot
Since the current through the conducting transistor is approximated in terms of a triangle, a triangular fit to the PMOS
transistor current is also sought. Since the PMOS
transistor will not start
conducting until the NMOS
transistor conducts, the expected starting time is equal to Td. The
upper time limit, Tu, which corresponds to the time that the PMOS
transistor stops conducting
occurs whenthe transistor enters its cutoff region. Hence, Tu occurs whenVin equals Vdd- Vtp for
PMOS
transistors. Since the input is assumed to be linear, Tu will equal (Vdd-Vtp)lOc. The area
then can be found to be:
A =
Ip~ (Tu - T
a)
2
0EQ21)
Using this area and previously established relationships, the new ground transfer curve is obtained
and plotted along with the old approximation to the curve in Figure 7. The PMOS
transfer characteristic is plotted in Figure 8 along with the calculated curve using HSPICEwith BSIMmodels.
As can be seen from these figures, the new triangle approximations are within five percent of the
peak values of the curves calculated by HSPICEcircuit simulation.
Current Simulation for CMOS
Circuits
40.00
.........................................................................................................
150.00
30.00
.....................................
li~
~..........................
,~,,~1 O0.O0--
r~50.00
.....
0.00
0.00
2.00
Time (ns)
4.00
o.oo
............
I..............
I..........
~.oo
z.oo
Time(ns)
FIGURE
7. GroundCurrent and its Approximation FIGURE 8. PMOS Current and its Approximation
3.3 Triangle Approximation with General Gates:
Nowthat a methodology has been derived for the inverter, it can be extended to a general combinational gate, A general CMOSgate is pictured in Figure 9 where the PMOSand NMOS
transistors are represented by blocks. In drawing this figure, Ip and I n are assumedto be the total current
that flows through their respective blocks. It is assumedthat only the n-block or the p-block are
dominating the conduction at any given time. This assumption implies that active load circuits
will not be properly handled. For now, also assume that the lumped capacitance on the output
node of the gate is the only capacitance that is associated with this gate. Under the current simplified modelling assumptions, this will be the case as long as there is not a significant amountof
interconnect between transistor nodes that do not correspond to the output node.
"~
Ivdd
Ignd ~
FIGURE 9. Typical
Gate Representation
CurrenlSimulationfor CMOS
Circuits
9
Whena gate follows this basic structure, the inverter example directly correlates. In a complex
gate, a transistor or groups of transistors are either in series or in parallel. If the switching transistors are in parallel, the block transconductance will be the sumof all the transconductances associated with the switching parallel transistors. If the switching transistors are in series and there are
m switching at a given time, the block transconductance will have the form:
block
CEQ22)
rn
i=l
With this in mind, the gate can be thought of as a complexinverter that could have a different
transconductance value for each input combination. It should be noted that a transistor’s transconductance should be scaled if the input transition times do not coincide with all the non-coincident
switching transistor inputs. The scaling factor is determined by the percentage of overlap between
the different input transitions. For the parallel case, the transistor that starts to conductfirst is used
as the base transition time for scaling. Onthe other hand, the series case uses the transistor that
starts to conduct last to determine the scaling factor. Since the base transistor is always the transistor that causes the dominant charging or discharging current to flow through the circuit, the
threshold voltage used in calculations is the threshold voltage that belongs to the base transistor.
Since general gates have more than one input, it is possible that the output node from the gate may
have voltage gIitches. A glitch is defined to be any instance for whicha node starts at an initial
state value and returns to that value without reaching the opposite state value. In rids methodology, glitches are divided into two subcategories: input glitches and output glitches. An input
glitch occurs whentwo inputs to a gate have overlapping switching times, but the input transitions
are in opposite directions. For example, one input of a two input nand gate makes ^1 transition
while the other makes a ^0 transition. An output waveformglitch occurs when the input waveform does not glitch, but the output waveformof the gate returns to its initial state without first
reaching its opposite state.
At this point, it is assumedthat an input glitch causes the current to and from the gate to be zero.
In general during an input glitch, the output voltage of a gate changes insignificantly (i.e., the
voltage does not change more than the turn-on voltage of the next gate). So, an input glitch is usually a localized phenomenon
internal to a gate and will not affect any of the gates that are attached
to its output. However,this assumption can cause the predicted current to be less than the actual
current. To correct this problem, a DCsolution can be found similar to the non-dominate current
that flows during an output transition. However, no specific methodologyhas been developed at
this time and the current contributed by an input glitch is presently ignored.
On the other hand, output glitches maycause a significant amountof current to flow. Since the
inputs makefull transitions, the triangular current associated with each transition can be determined. However,since a glitch occurs, the current waveformsoverlap. The less the overlap that
exists between the waveforms, the closer the outpu~ voltage comes to makinga full state transition. In somecases, this voltage is enoughto cause the gates on the output node to begin to con-
Current Simulation for CMOS
Circuits
10
duct. However,in general, the output glkch behaves more like an input glitch to the next gates.
Even though the next gates have had time to start conducting, their output will not have had
enough time to change significantly. Therefore, the current contributed by the output of the next
gate is ignored. However,the current caused by the glitching output is added to its power nodes.
For simplicity, the current contributed by the glitching node is assumedto be the sum of its overlapping triangular currents. This assumption maycause a slight overestimation of the current during the overlapping portion of the waveforms. However,this error is not significant because the
overlap between triangles is only a small percentage of each individual triangle which implies that
only small amounts of current are flowing.
3.3.1 Adding Internal Capacitance
Previously, it was assumedthat there was no internal capacitance in a gate. In general this is a
poor assumption. Anytime that there is metal interconnect between two transistors, there will be
an associated capacitance either to the substrate or to the well of the transistor. For now, the parasitic capacitances associated with the transistor itself wii1 not be taken into consideration because
this is a modelling issue which will be dealt with in Section 5.0.
Whenan internal node does have a capacitance value, there will be an amount of charge associated with the node during a transition. The amountof charge is equal to the voltage at the node
multiplied by the capacitance of the node. This charge must be discharged or charged to the power
node assuming that its value is different than that of the power node. If the charge found on the
capacitor charges or discharges, the output node is affected. The current needed to discharge or
charge the internal capacitors gets subtracted from the amount of current previously seen by the
output node. Therefore, the decreased current causes the output node to change for a longer period
of time, whichis the same as the minor short circuit current during the transition. Since the internal charge has the same affect as the short circuit current, the amountof charge found on the internal nodes will be added to the amountof area previously obtained for the short circuit currem.
Then the total area can be added to the original triangle. In this way, the original triangle approximation only has to be adjusted once instead of twice. However,this approach requires that each
300.00
......
200.00"’"~"200.00
......
150.00
......
100.00
......
~
100.00
......
50.00
.....
0.00
0.00
0.00
Time (ns)
FIGURE 10.
NANI) with
Coincident
Current Simulation for CMOS
Circuits
Inputs
4.00
Z O0
Time (ns)
3.00
FIGURE 11.
NOR with
Coincidem
lnpu[s
lI
350.00
.........................
25000
.......
300.00
..................................
200.00
......
250.00
................................
&15o.oo
....
ZO0.O0,................................
~100.00....
150.00
........................
100.00
..................
rj 50.00-0.00
0.00 "
4.0o
z.oo
0.00
0:00
2.00
Time (ns)
Time (ns)
FIGURE12. NANDwith Non.coincident
Inputs
complex gate have an amount of charge associated
all the secondary effects are taken into account.
4.00
FIGURE13. NORwith Non-Coincident Inputs
with each transition
that
must be stored until
Figures 10 and 11 show the results of coincident A0 transitions
for the inputs to a two input
NANDgate and a two input NORgate, respectively,
along with HSPICE predicted currents using
BS]2¢I models. Figures 12 and 13 show the results of non-coincident A0 transition
for both inputs
when applied to the same NANDand NORgates, respectively,
along with HSPICE predicted currents using BSINI models.
3.4 Nonlinear Input Voltages
Until now, it has been assumed that the input voltage has been linear with respect to time. However, the output voltage from an inverting stage can be shown to be nonlinear under the simplifying triangle approximation. In fact it has a piecewise quadratic appearance. However, due to the
triangle approximation, the input node to a gate is always piecewise linear with respect to the
input current. Therefore, the previous methodology must be reformulated.
Let it now be assumed that the input voltage has a piecewise linear
Iin = 0t (t-
(EQ23)
to) 0
over an interval of interest. Due to the simplified transistor
load on any of the nodes is capacitance. This implies that
V-in--
where Cm is the total
Current Simulation
current of the form:
model that is being assumed, the only
)2 )Io(t-to
Ci
n
(EQ24)
+
2Cin
load found on the input node.
for CMOSCircuits
12
Using
this equation for Vimthe first time point of the triangle, Td, can be obtained by setting V
m
equal
to
the threshold voltage of the transistor that is about to start conducting. Observe that T
d
mayhave to be solved recursively due to the fact that the input current maychange regions of linearization.
To find the second time point, T1, and the current value I1, Equation 8 must be reevaluated: Using
the new definition for Vm, the new relationship between Vin and Vout is given by:
~n~’Cin
(gin
-- Vtn)
--.
(EQ 25)
3IinCto
t
Again, this equation is only valid as long as Vout t>= Vin- Vm,therefore the end condition Vou
equals Vin - Vtn can be used to find Vout. If the three highest order terms of the Taylor series
expansion of ln(I+x) are used, a cubic equation can be obtained that will determine the values
Vout, Vm,and T1. However,it should be recalled that Iin is only valid over an interval and is a
function of tLrne over all the intervals. Therefore Newton-Raphson
iteration is used to determine
the correct current value and interval of interest. The current at this time, If, can be obtained by
solving the linear characteristic equation with the derived input and output voltages.
The third time point is again obtained using charge conservation and the triangle approximation.
4.0 Triangle Approximation Validity:
To find the triangle approximation, it was assumed that the current waveformwas following a typical ground current curve. Whatis meant by typical is that the gate has a small or moderate sized
load for its transistors sizes. For this condition to have been true, C.tot was assumedto be small
enough that the driving transistors were able to leave the saturation region before Vin reached its
steady state value. If Ctot were too large, it wouldcause the driving transistors to stay in their saturation r~gion even after Vm reached Vdd. Therefore, a critical load capacitance must be determined for each gate to ascertain whether or not the triangle approximation is valid.
Using Equation 9, a critical capacitance can be found for the output node. This value can then be
comparedto the load capacitance to determine whether a transistor is properly loaded, and if the
triangle approximation is still valid. For example, the critical capacitance for an NMOS
transistor,
Ccrit, can be found by setting Vm equal to Vddand Vout equal to Vdd- Vtn in Equation 9. Solving
for the capacitance, Ccrit:
~n~n (Vdd
Ccrit
-- Vm ) 3
CEQ 26)
=
3ocln {
1) -f-
n)~
(Vdd -- Vtn
1 -t-
knVdd
}
If )~is negligible,
Current Simulation for C~IOS
Circuits
13
1~n (V,~d _ Vt,)
Ccrit ~
(EQ 27)
3 IXVtn
If C.to t is greater than Ccrit the circuit designer maywish to change the design. Anytimethat a gate
is critically loaded, the circuit will not be able to achieve the fastest possible transition times.
However,if the designer does not wish to change the design, the triangular model can be slightly
altered. If the value of Ctot is larger than Ccrit, the current I n reaches a maximum
value INma.x and
remains there until Vout equals Vdd - Vm, where INmaxequals ~n(Vdd-Vm)2(1+ X(Vdd- Vm)).
current wave form then has a trapezoidal shape with respect to time. Using this expression for
INmax,a simpIer expression for the critical capacitance can also be obtained. Since the time at
which the triangular approximation is knownto start turning into a trapezoid, this time can be
used along with charge conservation to determine the new expression. The new expression is:
(T R -- Td) INmax
Ccrit
(EQ 28)
=
2Vtn
whereTR is the input transition dine. Note that the input transition time is the total time that it
takes the input to proceed from one input state to the next and not from the ten and ninety percent
points that are typically used. A similar expression can be calculated for PMOS
transistors. It
should be noted that, since the assumption was madeat Equation 9 that ordyone transistor block
was conducting at a time, the value for Ccrit is actually larger than what should be used in practice. Although results indicate that using the calculated Ccrit value does give results which are
usually within 20%of the peak value predicted by HSPICEeven when the load on the gate is
greater than its critical value (see Figure 14).
3oo.oo
......... ~............................................................................
i ................
200,00
......
150.00
.......
q00.00
......
50.00
......
0.00
0.00
20.00
40.00
60.00
Time (ns)
FIGURE 14. Inverter
Ground Current
CurrentSimulationfor CMOS
Circuits
with Large Load
14
Cgd
Vg
FIGURE
15. NewTransistor Model
5.0 Updated Transistor Model
A simplified transistor model has been used to develop the methodology thus far. However, the
simplified model is inadequate for any but the simplest of applications. A more complicated
model in general must be knplemented. A more realistic model can be found in Figure 15. This
model takes into account the parasitic capacitances associated with the gate capacitor overlapping
the other nodes. Also the sidewall capacitance due to highly doped source and drain regions can
be accounted for with this model. It should be noted that this model causes capacitors to be connected to every node. Therefore, any gate except the inverter will have internal capacitance associated with each node in the gate.
Due to the overlap gate capacitor, current can traverse from the gate to the drain or source. It is
assumedhoweverthat the current is controlled by the change of state on the gate. The reasons for
this assumptionare two fold. First, the gate voltage starts to change state before the voltage on the
source or drain begins to change. This means that the current flowing through the capacitors are
already established before the out-put state begins to change. Secondly, if the current is allowed to
be controlled by the source or drain transition, the input state is partially controlled by the out-put
state. This implies that previous stages would have to be updated after solving for stages that
occur after them. This is a second order effect that in general is negligible and will be ignored
since it is undesirable.
5.1 Finding ParameterValues
Until now, it was assumed that all of the model parameters are given. In general, howeverthey
have to be derived. Since the results of this methodology are being compared to HSPICEusing
BSIMparameters, the model parameters in general are obtained similarly to those found in the
BSIMmodel. All capacitor values are found the same way that linear capacitors are found for the
BSIMmodel. The threshold voltage is found in the same manner as the BSIMmodel with the
assumption that the drain to source voltage and the bulk to source voltage is zero. The channel
Current Simulation for CMOS
Circuits
15
length modulation factor, )~, is found by finding the equivalent level two SPICEmodel and using
the obtained value for )~. The fial parameter, [~, howeveris found quite differently.
To find [3, a HSPICEsimulation was needed to make it compatible to the BSIMmodel. An
inverter was simulated using HSPICEwith the desired BSIMparameters. The load capacitor of
the circuit was large enough so that the load was muchgreater than the predicted critical capacitance. In this case, the load capacitor was chosen to be ten time that of the expected critical capacdevice was then found by finding the time atwhich Vou
titance of the transistor. ~ for the NMOS
equals the initial output voltage, Vdd, minus the threshold voltage of the conducting transistor.
Since Vin had reached its final value, only the NMOS
transistor should be conducting. Equation 2
was then used to solve for ~ when)~ was set equal to zero and D was t he Sum of s ource c urrent
plus the bulk current of the transistor. ~ for the PMOSdevice is found in the same manner except
that the desired output voltage will be equal to the threshold voltage of the PMOS
transistor. This
methodfor finding ~3 implies that a fabricated test inverter that is critically loaded could be used to
obtain the same information and thus foregoing the HSPICEsimulation.
6.0 Results of Testing
In this section, the results from preliminary experimentation using the developed methodologyare
presented. For testing purposes, the methodolo~, was incorporated into a simulator called SIM.
The simulator was then tested on three different combinational circuits. The first circuit was a
chain of inverters with twenty gates, The second was the carry look-ahead part of an adder. The
third circuit was a parallel partial product multiplier.
Since it was shownthat single gates generally follow the desired trian&mlar approximation, it still
has to be demonstrated that gates still behave correctly under the new modelling assumptions, and
whether or not a gate can be driven by a nonlinear linear input voltage. Also, it has to be determined whether gates with more than two inputs are handled appropriately. Finally, it must be
determined ff the methodolog-y presented will truly decrease the time needed to analysis a given
circuit and whether or not this method, in general, is suitable for VLSIcircuits. To this end, the
following three examples were undertaken.
The first circuit that was tested was a chain of twenty inverters (see Figa~re 16). The capacitance
on each node was determined by the amount of metal interconnect between each gate. This circuit
was used to determine ff the delay times, with nonlinear input voltages being propagated, would
be approximately the same as the results predicted by HSPICE.Both the positive and negative
transitions were tested. At three nano-seconds, a ^0 transition with a two nanosecond rise time
Current Simulation for CMOS
Circuits
16
500.00
............
50.00
............
0.00
5.00
l 0.00
15.00
20.00
ZS.00
30.00
Time (ns)
FIGURE 17. Inverter
Chain Current
occurred followed by a ^1 transition with a two nanosecond rise occurring at ten nanoseconds.
The circuit was then allowed to return to its steady state. The results were then plotted in Figure
17 along with its HSPICEresults using BSIMmodels. As can be seen from the plot, the simulator
is able to approximate most of the current waveform predicted by HSPICE.The waveform transition times predicted by SIMare within three percent of the transition times predicted by HSPICE.
Also, the maximumcurrent of the predicted waveform is within ten percent of the maximumcurrent predicted by HSPICE.However, it should be noted that the maximumpredicted by SIM is
greater than the maximum
current predicted by HSPICE.Since the results are going to be used to
determine the affects of IR-noise and electromi~ation, it is better to have a waveformwhich is
greater than the actual waveform. Then if any re-desi~fing has to be done, it will over compensate
for the effects that the desig-ner is attempting to eliminate.
Since the simulator preformed adequately for the inverters chain, a more complicated circuit was
then tested. Figmre 18, shows the combinational circuit that was used. It is a carry generator used
in a look-ahead adder. This circuit was chosen due to the large diversity in gate sizing. Also, this
circuit is capable of producing input and output glitches. Fi~oaj_re 19 showsthe results of four different transitions that occur at 15 nanosecond intervals for both S1Mand HSPICE.As can be seen
from the figure, the two current waveformsare similar. The largest error between predicted current heights occurs during the fourth transition. This difference is mainly caused by the unaccounted for input glitching currents. However,if these inputs were a set of transitions that were
probable candidates for the worst effects of IR-noise and electromigration, the error in the fourth
transition would not matter. The reason for this is that transition one would be correctly chosen for
the transition that would cause the worst IR-noise, and transition three would be correctly chosen
to be the transitions that caused the worst effects of e)ectromigration. In Figure 19, these two transitions are within five percent of the maximumcurren~ predicted by HSPICE.and are within ten
percent of the predicted transition times.
Currcnl Simulationfor CMOS
CircuiLs
17
FIGURE 18. Carry
Look-Ahead Circuitry
4.00
............
~HSPICE
...... SIM
8.50
...........
3.00
.............
Z.O0
.............
~I.oo
.............
~.~
0.50
.............
-0.50
.............
-1.00
0.00
FI(;UI/E
10.00
19. Carry lxmk-Ahead Circuitry
Current Simulationfor CMOS
Circuits
ZO.O0
30 O0
Time(ns)
40.00
60.00
50.00
Currenl
18
0.00
o.oo
FIGURE20. Multiplier
s.oo
~o.oo ~s.oo
Time(ns)
zo.oo
zs.oo
~o.oo
3s.oo
Current
The fial circuit to be tested was a parallel partial product multiplier.
The multiplier allows a
eight-bit
number to be multiplied by a nine-bit number producing a seventeen bit output. The multiplier consists of 8 half adders, 48 full adders, 70 ANDgates, and 2 four-bk carry look-ahead
adders. The results of one transition
predicted by SIM along with the results obtained by HSPICE
using BSIM models are found in Figure 20. Notice that the maximum currents predicted by SIM
are again within five percent of those predicted by HSPICE.
Since SIM was able to approximate the expected waveform, its performance is required.
Table 1
shows results for the different simulations used during this experiment. They were all preformed
on a DECstation 3100. Looking at Table 1, at worst SIM was able to get a desired result thirtythree times faster than HSPICEwith the inverter chain, seventy-four times faster for the lookahead circuitry,
and ninety times faster for the multiplier. This implies that SIM’s times will not
increase as rapidly as HSPICE’s time as a function of the number of transistors.
Also note that
TABLE1. Comparison of SIM and HSPICE Times in Seconds
Circuit
No. inputs
Inverter
1
Chai~
Look-Ahead
9
No. Gates
20
30
No. Transistors
40
144
Circuitr3.,
Multiplier
17
700
2480
Simulator
1
2
HSPICE
13.3
20.2
SIM
0.4
0.5
HSPICE
37.0
SIM
0.5
HSPICE
SIM
Current
Simulation
for
CMOS Circui~-s
No. of transitions
3
4
5
61.9 88.5 114.1 144.4
1.2
0.6
0.9
1.6
3096.2 5195.7 7402.4 9595.3
26.9
51.1
71.4
105.7
19
SIMhas about the same gain as a function of transitions.
transitions where as SIMincreased 3.2 times.
HSPICEincreased 3.9 times for the five
7.0 Conclusions:
In this paper, a methodologywas presented that used a triangle approximation that estimated the
current waveformsproduced by a gate. It was demonstrated that this triangular approximation is
able to achieve results that are comparable to the results achieved by HSPICEusing BSIMmodels. Whenincorporated into a simulator, the new simulator was shownto have at least an order of
magnitude improvement in speed over HSPICE.However, currently this simulator is only able to
predict currents on a limited numberof circuits. In the future, a numberof issues will have to be
resolved to enable this simulator to handle general CMOS
technolog-y.
One of the first structures that have to be considered is the pass gate. Almost every CMOS
desig-n
has some type of pass gate structure associated with it. It is proposed that a pass gate can be handled similarly to any other gate. That is its current can also by approximated by a triangular current. However, the major difference between a pass gate and another CMOS
gate is that in general
there is no direct path to ground. Therefore, charge sharing between nodes will have to be taken
into account.
Next, a better methodwill have to be found to handle input glitches. In order to achieve this, partial transitions on a node will have to be incorporated into the existing methodolog-y.
Finally, a greater decrease in the amountof time a simulation takes can be achieved if a transistors
triangles are stored. The load on each node does not change. Therefore, it seems possible that each
transistor will have a few triangular waveformsassociated with it. It will be largely dependent
upon the voltage across the transistor’s drain and source and the transition time of the input. However, in general, the previous stage to a gate wilt generally drive the gate’s input with a limited
numberof different rise and fall times. Also, a gate has a limited numberof different voltages
found across its source and drain during sLrnulation. Therefore, a table could be formed during
simulation that will keep track of the different transitions that occurred up until that time. Then by
reusing previous results, a greater speed up should occur whenthere are manydifferent input transitions given in an input set. This new method would probably have an even greater effect if a
general method was found to determine a new triangular current when individual triangles are in
series and parallel.
Current Simulation
for CMOSCircuiks
20
8.0 References:
[I] F. Najm, R. Burch, E Yang, and I. Hajj, "CREST-A current Estimator for CMOS
Circuits,"
ICCAD-88, Digest of Tech. Papers, pp. 204-207, Nov. 1988.
[2] A. Deng, Y. Shiau, and K. Lob, "Time Domain Current WaveformSimulation of CMOSCircuits," ICCAD-88,Digest of Tech. Papers, pp. 208-211, Nov. 1988.
[3] H.J.M. Veendrick, "Short-circuit dissipation of static CMOS
circuitry and its impact on the
design of buffer circuits," IEEE Journal of Solid-State Circuits, Vol SC-19, No.4, pp.468-473,
Aug. 1984.
[4] V.D. A~awal and S.C. Seth, "Test Generation For VLSI Chips", Computer Society Press, pp.
67-94, 1988.
[5] M.R. Garey and D.S. Johnson, Computers and Intractabilio,."
Completeness, New York: W. H. Freeman, 1979.
A Guide to the Theo~3, of NP-
[6] R. Butch, E Najm, R Yang, and Dale Hocevar, "’Pattern-Independent Current Estimation for
ReIiability
Analysis of CMOSCircuits,"
ACM/IEEE25th Design Automation Conference, pp.
294-299, June 12-15 1988.
[7] David A. Hodgesand Horace G. Jackson, Analysis andDesign of Digital
Edition, New York: McGraw-Hill Book Company, pp 85-88, 1988.
Integrated
Second
Circuits,
[8] J. Hall, D. Hocevar, P. Yang, and M. McGraw,"SPIDER - A CADSystem For Modeling VLSI
Metallization Patterns", IEEE Trans. Computer-Aided Design, vol. CAD-6,pp. 1023-103 i. Nov.
1987.
Current Simulation
for CMOSCircuiLs
21