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Download 7.5 Design the circuit in Fig. P7.5 to obtain a dc voltage of +0.2V at
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7.5 Design the circuit in Fig. P7.5 to obtain a dc voltage of +0.2V at each of the drains of Q1 and Q2 when vG1 = vG2 = 0V. Operate all transistors at Vov=0.2 V and assume that for the process technology in which the circuit is fabricated, Vtn= 0.5V and µn Cox = 250 µA/V2. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, Q3,and Q4. What is the input common-mode voltage range for your design?