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COLORADO STATE UNIVERSITY
ECE 332: ELECTRONIC PRINCIPLES II
HOMEWORK 7
1. For an NMOS differential pair with a
common-mode voltage 𝑉𝐶𝑀 applied,
as shown in the figure,
let 𝑉𝐷𝐷 = 𝑉𝑆𝑆 = 1.0 𝑉,
𝑘 ′ 𝑛 = 0.4 𝑚𝐴/𝑉 2 , (𝑊/𝐿)1,2 = 12.5,
𝑉𝑡𝑛 = 0.5 𝑉, 𝐼 = 0.2𝑚𝐴, 𝑅𝐷 = 10𝑘Ω,
and neglect channel-length
modulation.
a) Find 𝑉𝑠𝑎𝑡 & 𝑉𝐺𝑆 for each transistor.
b) For 𝑉𝐶𝑀 = 0, find
𝑉𝑆 , 𝐼𝐷1 , 𝐼𝐷2 , 𝑉𝐷1 , and 𝑉𝐷2.
c) Repeat (b) for 𝑉𝐶𝑀 = +0.3 𝑉.
d) Repeat (b) for 𝑉𝐶𝑀 = −0.1 𝑉.
e) What is the highest value of 𝑉𝐶𝑀 for which 𝑄1 and 𝑄2 remain in saturation?
f) If current source I requires a minimum voltage of 0.2V across it to operate properly (i.e.
0.2V is its compliance voltage), what is the lowest value allowed for 𝑉𝑆 and hence for
𝑉𝐶𝑀 ?
2. For the PMOS differential amplifier shown in the
figure, let 𝑉𝑡𝑝 = −0.8 𝑉 and 𝑘 ′ 𝑝 (𝑊/𝐿) = 4 𝑚𝐴/𝑉 2 .
Neglect channel-length modulation.
a) For 𝑣𝐺1 = 𝑣𝐺2 = 0𝑉, find 𝑉𝑠𝑎𝑡 and 𝑉𝐺𝑆 for each of
𝑄1 and 𝑄2 . Also, find 𝑉𝑆 , 𝑉𝐷1 , and 𝑉𝐷2.
b) If the current source requires a minimum voltage
of 0.5V (compliance voltage), find the input
common-mode range.
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3. Design the circuit shown in the figure below to obtain a DC voltage of +0.2V at each of the
drains of 𝑄1 and 𝑄2 when𝑣𝐺1 = 𝑣𝐺2 = 0𝑉. Operate all transistors at 𝑉𝑠𝑎𝑡 = 0.2𝑉 and assume
that for the process technology in which the circuit is fabricated, 𝑉𝑡𝑛 = 0.5 𝑉 and 𝜇𝑛 𝐶𝑜𝑥 =
250𝜇𝐴/𝑉 2 . Neglect channel-length modulation. Determine the values of 𝑅, 𝑅𝐷 , and the 𝑊/𝐿
ratios of 𝑄1 , 𝑄2 , 𝑄3 , and 𝑄4 . What is the input common-mode voltage range for your design?
4. Design the MOS differential amplifier of the figure shown below to operate at 𝑉𝑠𝑎𝑡 = 0.25𝑉
and to provide a transconductance 𝑔𝑚 = 1 𝑚𝐴/𝑉. Determine the 𝑊/𝐿 ratios and the bias
current. The technology available provides 𝑉𝑡 = 0.8 𝑉 and 𝜇𝑛 𝐶𝑜𝑥 = 100𝜇𝐴/𝑉 2 .
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5. The figure below shows a circuit for a differential amplifier with an active load. Here 𝑄1 and
𝑄2 form the differential pair, while the current source transistor 𝑄4 and 𝑄5 form the active
loads for 𝑄1 and 𝑄2 , respectively. The DC bias circuit that establishes an appropriate DC
voltage at the drains of 𝑄1 and 𝑄2 is not shown. It is required to design the circuit to meet the
following specifications:
a)
b)
c)
d)
Differential gain 𝐴𝑑 = 80𝑉/𝑉
𝐼𝑅𝐸𝐹 = 𝐼 = 100𝜇𝐴.
The DC voltage at the gates of 𝑄6 and 𝑄3 is +1.5V.
The DC voltage at the gates of 𝑄7 , 𝑄4 and 𝑄5 is -1.5V.
The technology available is specified as follows: 𝜇𝑛 𝐶𝑜𝑥 = 3𝜇𝑝 𝐶𝑜𝑥 = 90𝜇𝐴/𝑉 2 ; 𝑉𝑡𝑛 = |𝑉𝑡𝑝 | =
0.7𝑉, 𝑉𝐴𝑛 = |𝑉𝐴𝑝 | = 20𝑉. Determine the required value of 𝑅 and 𝑊/𝐿 ratios for all transistors.
Also determine 𝐼𝐷 and |𝑉𝐺𝑆 | at which each transistor is operating. For DC bias calculations
you may neglect channel-length modulation. List the final results in a table with respect to
each transistor in the circuit.
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