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COLORADO STATE UNIVERSITY ECE 332: ELECTRONIC PRINCIPLES II HOMEWORK 7 1. For an NMOS differential pair with a common-mode voltage ๐๐ถ๐ applied, as shown in the figure, let ๐๐ท๐ท = ๐๐๐ = 1.0 ๐, ๐ โฒ ๐ = 0.4 ๐๐ด/๐ 2 , (๐/๐ฟ)1,2 = 12.5, ๐๐ก๐ = 0.5 ๐, ๐ผ = 0.2๐๐ด, ๐ ๐ท = 10๐ฮฉ, and neglect channel-length modulation. a) Find ๐๐ ๐๐ก & ๐๐บ๐ for each transistor. b) For ๐๐ถ๐ = 0, find ๐๐ , ๐ผ๐ท1 , ๐ผ๐ท2 , ๐๐ท1 , and ๐๐ท2. c) Repeat (b) for ๐๐ถ๐ = +0.3 ๐. d) Repeat (b) for ๐๐ถ๐ = โ0.1 ๐. e) What is the highest value of ๐๐ถ๐ for which ๐1 and ๐2 remain in saturation? f) If current source I requires a minimum voltage of 0.2V across it to operate properly (i.e. 0.2V is its compliance voltage), what is the lowest value allowed for ๐๐ and hence for ๐๐ถ๐ ? 2. For the PMOS differential amplifier shown in the figure, let ๐๐ก๐ = โ0.8 ๐ and ๐ โฒ ๐ (๐/๐ฟ) = 4 ๐๐ด/๐ 2 . Neglect channel-length modulation. a) For ๐ฃ๐บ1 = ๐ฃ๐บ2 = 0๐, find ๐๐ ๐๐ก and ๐๐บ๐ for each of ๐1 and ๐2 . Also, find ๐๐ , ๐๐ท1 , and ๐๐ท2. b) If the current source requires a minimum voltage of 0.5V (compliance voltage), find the input common-mode range. Page 1 of 3 3. Design the circuit shown in the figure below to obtain a DC voltage of +0.2V at each of the drains of ๐1 and ๐2 when๐ฃ๐บ1 = ๐ฃ๐บ2 = 0๐. Operate all transistors at ๐๐ ๐๐ก = 0.2๐ and assume that for the process technology in which the circuit is fabricated, ๐๐ก๐ = 0.5 ๐ and ๐๐ ๐ถ๐๐ฅ = 250๐๐ด/๐ 2 . Neglect channel-length modulation. Determine the values of ๐ , ๐ ๐ท , and the ๐/๐ฟ ratios of ๐1 , ๐2 , ๐3 , and ๐4 . What is the input common-mode voltage range for your design? 4. Design the MOS differential amplifier of the figure shown below to operate at ๐๐ ๐๐ก = 0.25๐ and to provide a transconductance ๐๐ = 1 ๐๐ด/๐. Determine the ๐/๐ฟ ratios and the bias current. The technology available provides ๐๐ก = 0.8 ๐ and ๐๐ ๐ถ๐๐ฅ = 100๐๐ด/๐ 2 . Page 2 of 3 5. The figure below shows a circuit for a differential amplifier with an active load. Here ๐1 and ๐2 form the differential pair, while the current source transistor ๐4 and ๐5 form the active loads for ๐1 and ๐2 , respectively. The DC bias circuit that establishes an appropriate DC voltage at the drains of ๐1 and ๐2 is not shown. It is required to design the circuit to meet the following specifications: a) b) c) d) Differential gain ๐ด๐ = 80๐/๐ ๐ผ๐ ๐ธ๐น = ๐ผ = 100๐๐ด. The DC voltage at the gates of ๐6 and ๐3 is +1.5V. The DC voltage at the gates of ๐7 , ๐4 and ๐5 is -1.5V. The technology available is specified as follows: ๐๐ ๐ถ๐๐ฅ = 3๐๐ ๐ถ๐๐ฅ = 90๐๐ด/๐ 2 ; ๐๐ก๐ = |๐๐ก๐ | = 0.7๐, ๐๐ด๐ = |๐๐ด๐ | = 20๐. Determine the required value of ๐ and ๐/๐ฟ ratios for all transistors. Also determine ๐ผ๐ท and |๐๐บ๐ | at which each transistor is operating. For DC bias calculations you may neglect channel-length modulation. List the final results in a table with respect to each transistor in the circuit. Page 3 of 3