Download eet 307 power electronics 2005-2006

EET 423 POWER ELECTRONICS 2
2006-2007
Q5.
(a) (i)
VOLTAGE MODE CONTROL
Ein
Vout
LPF
Dsw
RH
Vc
AV
+
+
kVout
RL
Vref
Vramp
PWM voltage mode control is the translation of an output voltage proportional analogue
signal into a pulse by comparison with a ramp. A range of commercially available pwm
controllers exist providing designers with a variety of performance characteristics.
Sometimes referred to as DIRECT DUTY CYCLE CONTROL
Vout
V
and out transfer functions are both dependent on Ein and require time therefore before
Vc
Ein
a response can be made.
Voltage Feedforward systems in which the ramp slope is not constant but varies dependent on
the input voltage can eliminate this.
(3 marks)
(a) (ii) CURRENT MODE CONTROL
Isense
Ein
Vout
LPF
Dsw
inner
current
loop
Vi
+ Vc
Vc = fn Vout
outer
voltage
loop
AV
+
RH
kVout
RL
Vref
Vi= fn Isense
The objective of current mode control is to control the ‘averaged’ inductor current.
A 2-loop control system is involved
OUTER voltage control loop and an INNER current control loop
EET 423 POWER ELECTRONICS
Q5 SOLUTION
1
Prof R T Kennedy
2006-2007
Operation is similar to voltage mode control in that an analogue voltage is translated into a
pulse width however in this case the VMC ramp is replaced by a voltage signal proportional
to the inductor current. This ‘injection’ of signal  terminology ‘Injected current mode
control’. The high speed current loop modulates the duty cycle within each cycle giving
improved frequency response and regulation stability.
The inner loop produces an analogue of the inductor or switch current, the up-slope of which
is compared with the current programmed level of the error voltage from the error amplifier
which is set by the outer loop.
The inductor current therefore follows (tracks) the error voltage
PEAK CURRENT MODE CONTROL has open loop stability problems at D>0.5 reulting in
the ramp requiring compensation
ic , vc
the outer loop controls ic , vc which in
turn controls the level at which the
inner loop limits Ipk
Vc  I L
PWM
Basically it is the inductor ripple peak current that is used , however the objective is to contol
V
the average current ( I av  out ).
R
Using peak sensing to control average has errors that are greater the higher the value of ripple
I pk  I out 
( Ein  Vout )  DswT
2L
ERROR
Reducing L has the disadvantage of requiring LARGER INDUCTANCE
Smaller inductance  smaller ripple but system then more susceptible to noise
Since the up-slope depends on the input voltage current mode control gives inherent voltage
feedforward and there is no requirement for an error signal to accommodate input voltage
changes.
The error amplifier has only to deal with load variations hence outer loop closed loop gain
can be reduced.
(3 marks)
EET 423 POWER ELECTRONICS
Q5 SOLUTION
2
Prof R T Kennedy
2006-2007
(a) (iii) ‘TRUE’ AVERAGE CURRENT MODE CONTROL
Isense
Ein
Vout
LPF
Dsw
inner
current
loop
Vc
outer
voltage
loop
Vi
+
CA
Vp
AV
+
Vramp
RH
kVout
RL
Vref
CA high gain integrating current error amplifier
Vp desired programmed level determined from the outer loop
Vi actual sensed current
Vc control signal: error amplifier output
Vr internal ramp
Ability to have increased low frequency inner current loop gain
Advantages:
high accuracy tracking of programmed level
functions even if operation changes from CCM DCM
no need for slope compensation
can be used to control any branch current in any topology
excellent noise immunity
(4 marks)
EET 423 POWER ELECTRONICS
Q5 SOLUTION
3
Prof R T Kennedy
2006-2007
(b) (i) CURRENT SENSING
RESISTOR sensing
Low resistance non-inductive resistors to avoid L
Tends to be lossy!
di
spikes
dt
I pk
Ipk
n
Rs
V pk 
I pk
n
 Rs
1: n
Lower losses  more efficient
isolation
more expensive
Switch current is often sensed as an alternative to inductor current
spikes and oscillation can occur due to
inter-winding capacitance
and
pn rectifier reverse recovery current
C-R filtering can eliminate / reduce
(4 marks)
(b) (ii) LEADING EDGE BLANKING
Leading edge blanking (LEB) causes the PWM
comparator to be ignored for a fixed amount of time
after the start of the pulse. This allows noise inherent
with switched mode power conversion and current
sensing to be rejected. The PWM ramp input may not
require any filtering as result of leading edge blanking.
(2 marks)
EET 423 POWER ELECTRONICS
Q5 SOLUTION
4
Prof R T Kennedy
2006-2007
(c) MOSFET GATE DRIVE WAVEFORMS
The values of the capacitances are determined by the structure of the MOSFET, the materials
involved, and by the voltages across them.
Capacitances Cgs and Cgd, vary with the voltage across them because they are affected by
depletion layers within the device.
The change in Cgd with drain-to-gate voltage can be as much as a factor of 100 or more.
Cgs has only a small voltage change across it compared to Cgd and consequently a small
capacitance change.
During turn-on and turn-off when traversing the active region of the Load Line the device is
effectively an amplifier and the MILLER EFFECT significantly increase the drain gate
capacitance resulting in the flattened regions.
INDUCTIVE LOADS
Ids from Irect, reverse recovery
IDS
Irect
Irect, reverse recovery
RESISTIVE LOADS
(4 marks)
(20 marks)
EET 423 POWER ELECTRONICS
Q5 SOLUTION
5
Prof R T Kennedy
2006-2007