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Analog Integr Circ Sig Process (2013) 75:67–74
DOI 10.1007/s10470-012-9994-5
A very high performance self-biased cascode current mirror
for CMOS technology
Maneesha Gupta • Bhawna Aggarwal
Anil Kumar Gupta
•
Received: 8 July 2012 / Accepted: 19 November 2012 / Published online: 24 December 2012
Springer Science+Business Media New York 2012
Abstract This paper presents a novel high performance
self-biased cascode current mirror (CM) for CMOS technology. The proposed circuit shows a resistance compensated high bandwidth CM operating at low voltages. This
circuit uses super cascode configuration to obtain high
output impedance required for high performance of CM.
Active implementation of passive resistances of the proposed circuit is shown. The simulations of proposed CM
are carried out by Mentor Graphics Eldospice based on
TSMC 0.18 lm CMOS technology, for input current range
of 0–500 lA. A bandwidth of 2.26 GHz, input and output
resistances of 679 X and 482 MX respectively, are
obtained with a single supply voltage of -1 V.
Keywords Low voltage CMOS analog integrated
circuits Cascode current mirror High swing operation Self-biased current mirror Super-cascode technique Active implementation
1 Introduction
A current mirror (CM) is a circuit designed to carefully
generate a true or scaled replica of current flowing through
M. Gupta
NSIT, Delhi, India
e-mail: [email protected]
B. Aggarwal (&)
MAIT, Delhi, India
e-mail: [email protected]
A. K. Gupta
NIT, Kurukshetra, Haryana, India
e-mail: [email protected]
one active device, by controlling the current in another
active device, regardless of changes in loading. CMs are
used as basic building blocks for current amplification,
biasing, active loading and level shifting in almost all
analog and mixed circuits such as OTAs, CCIIs, OMAs,
CFOAs, analog filters etc. Efficient designing of CMs help
in improving the overall performance of these systems. The
most important parameters of CMs are accuracy, input/
output compliances, input/output impedances, bandwidth
and linearity. To improve the CM performance and make it
compatible with the present industry trends, various
topologies have been suggested earlier. Level-shifter
technique is used to lower the compliance range, but it
requires additional circuitry to compensate the extra offset
introduced in the current, thereby increases the circuit
complexity and power requirement [1, 2]. The CMs based
on FGMOS technique have the problems of charge trapping and poor bandwidth due to a lot of parasitic capacitances involved [3, 4]. Bulk-driven based CMs too suffer
from poor bandwidth and reduced swing [5–7]. Koliopoulos et al. in [8] and Laoudias et al. in [9] have suggested
CMs with low compliance voltage requirement. However,
these CMs have the problem of accuracy in current
matching.
Conventionally transistors in cascode configuration are
used to increase the output resistance and to improve the
accuracy of a CM. However, cascoding the transistors
increases the requirement of the supply voltage and also
reduces the input/output compliance range, which makes it
non-compatible with today’s technology trend.
Here, a novel high performance cascode CM has been
proposed. The wide swing characteristic of self-biased
cascode CM is utilized and its bandwidth is enhanced using
resistance compensation technique. Super-cascode configuration has been used at the output side of the CM, to
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Analog Integr Circ Sig Process (2013) 75:67–74
improve the output impedance of the proposed circuit.
Finally, active replacement of passive resistances used in
the developed circuit has been carried out, so that it is
compatible with presently used full monolithic integrated
circuit technology. The paper is organized as follows: Selfbiased cascode CM is explained in Sect. 2. Application of
resistive compensation technique to increase bandwidth is
discussed in Sect. 3. In Sect. 4, implementation of supercascode technique for improving output impedance is
shown. Active implementation of the resistances of the
proposed CM is explained in Sect. 5. Section 6 deals with
simulation results using Mentor Graphics Eldospice based
on TSMC 0.18 lm CMOS technology, which is followed
by conclusions drawn.
iB
iB
iOUT
iIN
+
M3
+
M1
+
vIN
VON+VT
vOUT
M4
-
+
M2
VON+VT
-
-
2 Self-biased high swing cascode current mirror
VSS
To obtain high performance CM, a lot of work has been
carried out in literature. Various CMs working in different
regions of operation of MOSFET, namely saturation [8–
10], triode [11, 12] and subthreshold [13], have been
reported time to time. The CMs using MOSFETs operating
in saturation mode have higher transconductance (gm) than
those based on MOSFETs operating in triode or subthreshold mode. This leads to higher bandwidth and better
input and output impedances. For such CMs, all MOSFETs
should satisfy the condition:
VDS VGS VT
ð3Þ
Also, compliance voltage of the output terminals of this
cascode CM is given as:
Vout;min ¼ VT þ 2VON
ð4Þ
The self-biased high swing cascode current mirror
(SBCCM) is shown in Fig. 2 [15]. In SBCCM, if the value
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+
iB
+
R
vON
iOUT
-
+
M3
+
vIN
M4
-
M2
vOUT
VON+VT
M1
+
-
-
VON+VT
VSS
Fig. 2 Self-biased high swing cascode current mirror
ð2Þ
Then, the input compliance voltage of a cascode CM
shown in Fig. 1 is given as [14]:
Vin;min ¼ 2VT þ 2VON
iB
iIN
ð1Þ
where, Vxy represents the voltage drop across x and y
terminals (through out this paper) and VT is the threshold
voltage of the MOSFET.
This shows that the input/output compliances of a CM
depend on the minimum voltage drop required by the
MOSFETs of the mirror to operate in saturation mode.
High compliance range is useful for accurate operation of
CM with low power supply voltages. The accuracy of low
voltage analog circuits will be enhanced when designed
using these CMs.
Let,
VDSðminÞ ¼ VGS VT ¼ VON ðsayÞ
Fig. 1 Simple cascode current mirror
of resistance R is chosen in such a way that the potential
drop across it is ‘VON’, then in this circuit the values of
input and output compliance voltages are ‘VT ? 2VON’
and ‘2VON’ respectively. This show an improvement by a
factor of ‘VT’ as compared to cascode CM, which leads to
lowering of supply voltage required by the CM for its
proper operation. The SBCCM provides the advantage of
high output resistance and high voltage swing along with
low power consumption. The input and output impedances
of SBCCM, shown in Fig (2), respectively are given as:
Analog Integr Circ Sig Process (2013) 75:67–74
rin 1
þR
gm4
69
ð5Þ
rout ðr01 r02 gm2 Þ
ð6Þ
where, gmi is small signal transconductance of NMOS Mi
and roi is small signal output resistance of NMOS Mi. Here
i = 1, 2…,4.
where Cgsi represent gate-source capacitance of NMOS Mi.
Bandwidth of this second order low pass system is given
as:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
g g
0
m2 m4
x0 ¼
ð8Þ
Cgs2 Cgs1 þ Cgs4
Let
Cgs1 ¼ Cgs4 ¼ C1 and Cgs1 ¼ Cgs2 ¼ C2
rffiffiffiffiffiffiffiffiffiffiffiffiffiffi
gm2 gm4
0
x0 ¼
2C1 C2
3 Bandwidth extension of SBCCM
Bandwidth is one of the most important features of any CM. It
affects the overall speed of the device which incorporates the
CM. In this section, resistive compensation method to increase
the bandwidth of SBCCM without influencing its DC characteristics is presented [16, 17]. The resistance compensated circuit of SBCCM (proposed-I circuit) for achieving higher
bandwidth is shown in Fig. 3. In this circuit, a compensating
resistance ‘R’ is added between the gates of primary pair
transistors M1 and M4, to enhance the bandwidth. The response
of the CM gets delayed due to introduction of the compensating
resistance. It introduces a zero in transfer function which cancels off the delay with proper choice of resistance value.
The transfer function of non-compensated SBCCM
shown in Fig. 2, neglecting input and output capacitors and
conductances, is given as:
gm2 gm4
ggm1
m4
Cgs2 ðCgs1 þCgs4 Þ
0
AI ðsÞ ¼
ð7Þ
gm2
gm2 gm4
m1 þgm4
s2 þ s Cggs1
þ
þ
þCgs4
Cgs2
Cgs2 ðCgs1 þCgs4 Þ
iB
iIN
ð9Þ
ð10Þ
Using similar assumptions as employed to derive (7), the
small signal model for bandwidth calculation of SBCCM
with resistance compensation is shown in Fig. 4.
From the circuit it can be analyzed that:
iout ðsÞ ¼ gm2 v15
ð11Þ
v12
iin ðsÞ ¼ sCgs2 v15 þ sCgs3 v13 þ
R
v12
v24
¼ sCgs1 v2 þ
þ gm3 v13
R
R1
v24
¼ sCgs4 v4
R1
ð13Þ
gm3 v13 ¼ gm4 v4 sCgs3 v13
ð15Þ
gm2 v15 ¼ gm1 v2 sCgs2 v15
ð16Þ
ð12Þ
ð14Þ
Combining and solving above equations we get:
iout ðsÞ
iin ðsÞ ¼ gm2
2
s Cgs1 Cgs4 R1 þ sCgs1 þ sCgs4 þ gm4
sCgs2 þ
sR1Cgs4 þ 1
gm2 þ sCgs2
ð17Þ
gm1
iB
This can be simplified as:
R
iOUT
6
Cgs2
M3
M2
1
Cgs3
R
gm3v13
gm2v15
5
iin
2
R1
3
R1
M1
M4
iout
Cgs1
gm1v2
gm4v4
4
Cgs4
VSS
Fig. 3 Resistance compensated SBCCM (proposed-I)
Fig. 4 Small signal model for calculating bandwidth of resistance
compensated SBCCM
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70
Analog Integr Circ Sig Process (2013) 75:67–74
gm1 gm2 sCgs4 R1 þ 1
iout ðsÞ
¼ 3
2
iin ðsÞ
s Cgs1 Cgs2 Cgs4 R1
þ s Cgs2 Cgs4 R1gm1 þ Cgs1 Cgs4 R1gm2 þ Cgs1 Cgs2 þ Cgs2 Cgs4
þs Cgs2 gm1 þ Cgs1 gm2 þ Cgs4 gm2 þ Cgs2 gm4 þ gm2 gm4
The mid-band gain, as obtained by substituting s = 0 in
(18), is given as:
iout
gm1
¼
iin
gm4
ð19Þ
This is same as that of un-compensated case as can be
calculated using (7).
Substituting (9) in (18) and simplifying, we get:
ð18Þ
obtained by using resistive compensation technique. This
was obtained by initially transforming a 2-pole low pass
system into a 3-pole and 1-zero low pass system by
resistance compensation technique. Then, finally
cancelling the introduced zero with the dominant pole
which can be easily obtained by proper choice of the
compensating resistance.
1
g
g
s
þ
m1
m2
C1 R1
iout ðsÞ
¼
gm1
gm2
2gm2
gm2 gm4
2
iin ðsÞ
m4
3
2
C1 C2 s þ s C1 þ C2 þ C1 R1 þ s gm1C2þg
þ
þ
2
C1 C2 R1
R1
C C2 R1
1
1
This is a transfer function of third order low pass system
with 1-zero and 3-poles.
Now, if
R1 ¼
1
gm4
ð21Þ
Then, (20) can be factorized as:
iout ðsÞ
gm1 gm2
¼
g
iin ðsÞ
m1
C1 C2 s2 þ s
þ gm2 þ
C1
C2
1
C1 R1
þ C1gCm22 R1
C1 C2
In proposed-I circuit shown in Fig. 3, the bandwidth has
been improved a lot. Also being a circuit of cascode configuration, its output resistance is high. But it can be
iB
iB
ð23Þ
iB1
iIN
R
iOUT
M6
M2
M3
M5
C1 C2
This is a transfer function of a second order low pass
system. From (23) the bandwidth of resistance
compensated SBCCM can be given as:
rffiffiffiffiffiffiffiffiffiffiffiffiffiffi
gm2 gm4
x0 ¼
ð24Þ
C1 C2
Comparison of (10) and (24), shows that an
improvement by a factor of H2 in bandwidth has been
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4 Implemetion of super-cascode configuration
on proposed-I circuit to achieve high output
impedance
ð22Þ
On choosing R1 = 1/gm4, the zero introduced due to
resistance compensation gets cancelled with the dominant
pole, thereby reducing the transfer function to a second
order low pass system.
Relation (21) can be used to modify (22) as:
iout ðsÞ
gm1 gm2
¼
gm1 C2 þgm2 C1 þgm4 C2
iin ðsÞ
2
C1 C2 s þ s
þ gm2 gm4
ð20Þ
R1
M4
M1
VSS
Fig. 5 Resistance compensated SBCCM with high output resistance
(proposed-II)
Analog Integr Circ Sig Process (2013) 75:67–74
71
iout
1
3
iB
4
iB
iB2
iB1
r04
r06
gm4(-v2)
gm5v32
iIN
r05
gm6v1
iOUT
M6
M10
+
2
2
vout
-
M5
M3
M2
M9
M1
M8
r02
M7
M4
Fig. 6 Small signal model for calculating output resistance of
proposed-II circuit
VSS
Fig. 7 Final proposed high-performance self-biased cascode current
mirror (proposed-III)
improved further by using super cascode configuration [18,
19] at the output side. The introduced output stage uses
MOSFETs M5, M6 and current source iB1, as shown in
Fig. 5. The supply voltage requirement of this circuit is
same as that of proposed-I circuit. The small signal model
for calculating output resistance of this proposed-II circuit
is shown in Fig. 6.
vout
rout ¼
ð25Þ
iout
From Fig. 6
iout ¼ gm5 v32 þ
vout v2
r05
ð26Þ
v2 ¼ iout r02
ð27Þ
v3 ¼ r06 gm6 v1
ð28Þ
v2 v1 ¼ r04 gm4 v2
ð29Þ
Simplifying (26)–(29), we get:
1
vout
iout 1 þ gm5 r06 gm6 ð1 þ gm4 r04 Þ þ gm5 þ
r02 ¼
r05
r05
5 Final proposed high performance CM circuit
with passive resistors replaced by active ones
In full monolithic integrated circuits, passive resistances
are made of poly-silicon. They consume a large amount of
chip area and have rather higher tolerances. Thus, their
utilization in any integrated circuit is not appreciable. At
the same time, tracking of the MOS transconductance,
which is highly dependent on process parameters and
temperature, by passive resistance is quite difficult. Figure 7 shows the final proposed circuit, which has been
obtained by the active implementation of all the passive
resistances appearing in the proposed circuit of Fig. 5.
In this final proposed circuit, resistor R1 has been realized using a MOSFET M7 in triode region and MOSFETs
M8 and M9 in saturation region [20]. The channel resistance of M7 needs to match 1/gm4 for optimum bandwidth.
The channel resistance of M7 operating in triode region can
be given as [14]:
r07 ¼
ð30Þ
Now, since
gm r 0 1
Thus (30) can be written in simplified form as:
vout
gm4 r04 gm5 r05 gm6 r06 r02
rout ¼
iout
ð31Þ
ð32Þ
From (32), it can be seen that by using super-cascode
structure, the output resistance of the proposed-II circuit
becomes very high (theoretically in GX range). However in
actual practice it is limited due to drain-substrate leakage
currents at the drain of MOSFET M5.
ln Cox WL
1
Vgs7 VT
ð33Þ
where all symbols have their standard meaning.
Also, resistor R used in the proposed-II circuit of Fig. 5
has been realized using MOSFET M10 as MOS diode, in
Fig. 7. The small signal resistance of such a MOS diode is
given as [12]:
r10 1
gm10
ð34Þ
Equations (33) and (34) indicate that the active
resistances shown in the proposed-III circuit are
dependent on the aspect ratios of the MOSFETs M7 and
M10. Thus, the desired voltage drop required in the circuit
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Analog Integr Circ Sig Process (2013) 75:67–74
Fig. 8 Output versus input
current transfer characteristics
curve of the circuits
Fig. 9 Curve showing current
transfer accuracy of the circuits
Fig. 10 Frequency response
representing bandwidth of the
circuits
and cancellation of dominant pole can be achieved by
varying the aspect ratios of these MOSFETs. The circuit
shown in Fig. 7 is the final proposed circuit of the
improved high performance CM. This proposed low
voltage CM has higher bandwidth, a very high output
123
resistance and improved current matching characteristics.
In this proposed circuit, the passive resistances have been
replaced by active ones and for a wide range of operation,
its output current is shown to be matched with input current
with very high degree of accuracy.
Analog Integr Circ Sig Process (2013) 75:67–74
73
Table 1 Comparative results
Performance factor
SBCCM
[10]
Proposed-I
Proposed-II
Proposed-III (final)
Range (lA)
0–500
\10
0–500
0–500
0–500
rin (X)
925
100
789
661
679
rout (MX)
0.879
200
0.768
326
482
BW (GHz)
1.68
0.04
2.469
NA
2.262
Supply voltage (V)
-1
1.2
-1
-1
-1
6 Simulation results
In this section, Eldospice simulation results for proposed and
other circuits have been presented. All of the simulations are
carried on Mentor Graphics Eldospice based on TSMC
0.18 lm CMOS technology, using a single supply voltage of
-1 V. For all the proposed circuits, aspect ratios of the
transistors (if used) are M6 = 0.18/0.18, M7 and M10 = 10/
0.18 and for rest of the MOSFETs aspect ratio is equal to
1/0.18. For all the DC analysis, iIN is varied from 0 to 500 lA.
Figure 8, shows the output vs. input current characteristics of SBCCM and all the proposed circuits. As shown in
this figure the proposed circuits exhibit great degree of
accuracy for a wide range of operation, making them
suitable for very low voltage applications. Also the current
transfer characteristics accuracy in percentage is shown in
Fig. 9. This figure reveals the fact, that final proposed
circuit has very low current transfer error (less than 0.5 %)
for the maximum range of operation. Furthermore, it
reflects that the maximum error in current transfer is limited to 2 %, that too for very low current values.
The frequency response of the conventional and proposed CMs is shown in Fig. 10. As reflected in this figure,
the bandwidth of the final proposed CM is 2.26 GHz. The
simulated values of rin and rout of the final proposed high
performance CM are 679 X and 482 MX respectively.
These values along with the corresponding values of other
circuits of this paper are tabulated in Table 1.
Besides, simulated results are compared with [10] to
prove the robustness of the proposed CM. These comparative results are summarized in Table 1. These results
illustrate the fact that bandwidth has improved considerably thereby increasing the working speed of the IC. Furthermore, the proposed circuit is able to operate over a
wider range (0–500 lA) in comparison to [10]. Operation
of the proposed circuit, with such a low voltage for a broad
current range and higher bandwidth along with its simple
structure can be considered as a significant achievement.
7 Conclusions
A novel self-biased cascode CM with very high performance characteristics has been introduced and verified with
the help of simulations. Bandwidth enhancement by a
compensation resistor between the gates of the primary
transistor pair of CM is shown. Improvement in output
resistance has been carried out by implementation of supercascode configuration at the output side. The active realization of the resistances, to overcome the drawbacks of
passive components has also been discussed. The proposed
saturation region CM, where all required resistances have
been replaced by active components, shows high degree of
accuracy over a wide input current range. Small signal
analysis has been carried out at each step and the results
have been validated using Mentor Graphics Eldospice
based on TSMC 0.18 lm CMOS technology using -1 V
supply voltage.
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Maneesha Gupta received her
B.E. and M.E. in Electronics &
Communication
Engineering
from Government Engineering
College, Jabalpur in the years
1981 and 1983, respectively.
She received her PhD. in Electronics Engg. from Indian Institute of Technology (IIT), Delhi
in 1990. Dr. Gupta served as
lecturer in various esteemed
institutes of India, for the period
1981-1998. Since 1998, she is
with Netaji Subhas Institute of
Technology, New Delhi and is
presently serving as Professor in, Electronics and Communication
123
Engineering Department in the same institute. Her teaching and
research interests are Switched Capacitors Circuits and Analog Signal
processing.
Bhawna Aggarwal was born in
1980. She received her B.E. in
Electronics & Communication
Engineering from Indira Gandhi
Institute of Technology, Delhi
in 2002, M.E. in Electronics &
Communication
Engineering
from Delhi College of Engineering, New Delhi in 2006 and
is currently involved in PhD.
work, in NIT Kurukshetra. Her
area of research is low power
design techniques. She is currently working as Assistant
Professor in Maharaja Agrasen
Institute of Technology, Sec 22, Rohini, New Delhi-110086.
Anil Kumar Gupta received
B.Tech. (ECE) from G.B.Pant
University of Agriculture and
Tecnology in 1972. He received
M.Tech. and Ph.D. in Electrical
Engineering from Indian Institute of Technology, Kanpur
in the years 1974 and 1985
respectively. He served as
Assistant Station Engineer in
All India Radio during the period 1974-78. Since 1985, he is
with National Institute of Technology, Kurukshetra where he is
presently serving as Professor,
Electronics and Communication Engineering for the last thirteen
years. His areas of interest are Semiconductor devices and Technology, Embedded systems, Instrumentation and VLSI Design.