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ECE 6332: Project Proposal
Aatmesh Shrivastava and Alicia Klinefelter
A Stable System Clock Generator Using Reference Clock Sampling
INTRODUCTION
A system clock for an SOC is generated using an off-chip crystal oscillator which provides a
reference clock and a phase locked loop which tracks the frequency and phase of the reference
clock. Crystal oscillators typically have very stable frequencies over temperature and voltage
variations which makes them a prime choice for reference clock generation. However, a crystal
oscillator consumes significant amounts of power which is proportional to the frequency. In
order to reduce the power dissipated in the crystal oscillator, we propose a scheme for
generating a system clock using a frequency locked loop. During the start-up phase, the FLL
builds up the frequency using a reference clock from the crystal oscillator. Once the oscillation
has built up and locked to a reference frequency, a part of the block is disabled along with the
crystal oscillator which would save a lot of power. Oscillation is carried out using a VCO and the
output of the DAC. The DAC is controlled using a PTAT to compensate for on die temperature
variation.
DESIGN COMPONENT
We eventually hope to put the design on the next revision of the BASN chip and will be
completing it in the IBM 130nm technology. We are going to try to improve on existing clock
generator architectures by implementing the clock generator using frequency-locked loop
architecture. Also, each block will be designed with achieving very low power in mind. The
speed at which the circuit latches the frequency and settles to a value is not as important as the
accuracy and power consumption. We will also need to discuss how the control signal for the
blocks will be generated for this application (BASN chip revision II). The following blocks will be
designed for the system:
F to V Converter:
A frequency to voltage converter, or FVC [2], is used to generate a voltage corresponding to a
frequency of oscillation. The higher the frequency, the lower the output voltage will be and so
the FVC can be viewed as an inverting amplifier.
The design is incorporated using a switching current source and switched capacitor scheme.
ADC/DAC:
We are designing a low-power (goal of 100nW) ADC and DAC to have 3-4mV resolution. Since
this circuit will be designed with the BASN chip application in mind, the operating voltages will
be from 1V. Using a 10-bit representation, these voltages can be covered with a 3-4mV
resolution. The goal of having the ADC is to transform the incoming voltage to the digital
domain. Within the digital domain, a bank of registers can be used to maintain the voltage. This
voltage will then be transformed back into the analog domain for further processing. This
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transformation will result in some quantization error that might have the ability to dramatically
affect the frequency after it goes through the frequency-to-voltage conversion.
There are two stages within most ADCs: sampling and quantizing. Sampling is performed with a
sample and hold circuit, while quantizing is usually performed with a series of comparison
circuits. Comparison CMOS circuits can be large and care needs to be taken when designing
with them since the more resolution desired implies more comparison stages. Since a majority
of the quantization stage is composed of them, one of the goals for creating the ADC is finding
an accurate, low-power comparator. Similarly, for sampling, we want to find a low-power
sample-hold circuit.
The most common architecture is a successive approximation (SAR) architecture, but this only
works for low resolution applications. It is based on having a series of capacitors where each is
twice are large are the previous. If the application requires a fine resolution, the capacitor sizes
can become large and then our small area constraint might be violated [4].
A ΣΔ ADC is used often for accurate and low-power applications and they can achieve a high
resolution for a low input frequency [5]. This scheme involves slowly placing charge
Error Amplifier:
The error amplifier is a folded cascade operational amplifier with source follower at the final
stage. The target gain for this amplifier is 100dB and phase margin is 80 degrees. The
quiescent current is around 300nA and this block will be disabled in the steady state operation.
VCO:
The voltage controlled oscillator is a ring oscillator based architecture where amplifier output
controls the frequency of oscillation. The higher the voltage, the higher the frequency of
oscillation will be.
PTAT:
A PTAT [3] provides a current that increases with temperature.
In our design we have a VCO that gives a frequency output corresponding to an input voltage.
The drive of the MOS device decreases with temperature so in order to compensate for this
effect we will add a PTAT current to the ADC’s output which will give a constant current over a
wide range of temperatures. This will help in controlling the drift.
RESEARCH
COMPONENT
There are many clock generation circuits and architectures that have been completed that use
phase-locked or delay-locked loops. Phase-locked loops are most frequently used in high speed
applications, which are design is relatively not. The circuit we are proposing to design uses a
frequency-locked loop, which is infrequently used for this application. Also, most clock
generation circuits do not include the ADC/DAC block that we have included. Since this block
will introduce quantization error that will need to be dealt with, this is considered a novelty.
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In the case that the voltage from the DAC drifts with temperature, we are including a PTAT
circuit that will vary the current coming from the DAC depending on the absolute temperature.
PTATs are circuits
Our primary concern when constructing and testing the system is to verify that it is extremely
low power. The goal of the project is to generate an accurate clock signal that consumes much
less power than a crystal, so we need to make sure that this occurs.
SIMULATIONS
TO
COMPLETE
We plan to extensively test the individual blocks to verify they work on their own. One set of
simulations will be the testing of these blocks.
Since the ADC/DAC will introduce quantization error within the circuit, we plan to simulate the
system without these components to see an ideal view of how the circuit will operate.
After the ADC/DAC system has been inserted, we would like to measure the amount of error
that is introduced to the system by comparing the new system with the system without the
ADC/DAC. Stability of the error amplifier might also be an issue with the delay introduced by the
ADC/DAC, but this can be accounted for and eliminated through modification of the error
amplifier to change the poles of the current design. There also will be a very small oscillation at
output of frequency to voltage converter in the feedback loop due to quantization errors in
ADC/DAC block. This oscillation will be tolerated as it’s very small and any effort to fix it will be
difficult to justify due to the increase in area the fix would create.
We will also complete simulations to estimate energy/power of individual blocks and the entire
system. If time permits after we complete the layout, we would want to do a simulation of the
system to account for any parasitic capacitances and resulting delays.
PROOF OF CONCEPT
Conceptually, the design will work as expected due to the following:
If we look at the labeled nodes above, we will describe at each point what we expect to see from
the circuit. As the frequency of the RF source/crystal increases, we expect to see the voltage at
the output of the F to V converter decrease (and vise versa) at A. This voltage gets converted
into the digital domain for storage and back into the analog domain to continue processing at B.
This voltage is used to control the VCO that generates a new frequency proportional to the input
voltage at C. This newly generated frequency is the output of the circuit. It also gets fed into
another F to V converted as part of a feedback loop to the error amplifier at D. The error
amplifier will compare this newly generated frequency with the reference frequency, and will
generate an error voltage that will eventually move the feedback voltage towards the reference
voltage (it will settle) as seen at point E.
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PTAT
Clock coming
from crystal or
RF source
F to V
Converter
A
_
C
B
Error Amp.
E
ADC
Register
Block
DAC
VCO
+
control
D
F to V
Converter
out
At this point the reference frequency from the RF source or crystal is locked and the source can
be turned off.
See attached for simulations that include the system not including the ADC/DAC system.
EXPECTED
OUTCOMES
We expect to have a circuit that comparable or lower in power than existing clock generator
circuits. We are also concerned with the area of the resulting layout and we seek to minimize
this. We hope that we can eventually
SCHEDULE
As mentioned in the first design review, we are going to carry out the design in four phases:
 Phase I: We will design the individual blocks. Some of the work has been completed
and few blocks are done.
o


Complete individual simulations for each block to verify functionality.
Phase II: Connecting the blocks together. This will require going back to phase-I to
incorporate minor tweaks in the designed components
o
Discuss and generate the logic for the control signal.
o
Complete simulation of entire system.
Phase III: Complete layout of the blocks and then run a post-layout extracted netlist
(iterate if required).
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o

Verify that the layout is as dense as possible so that area can be reduced.
Phase IV: Documentation of the results for the presentation and final report (if time
permits, we will complete silicon characterization (if this can be scoped)).
o
Combine results to complete conference style paper.
o
Prepare presentation for the class.
The way we have allocated our time is shown below in the Gantt chart. Layout will take a
considerable amount of time to complete for all blocks. Although this is not required, since we
plan to add the circuit to the next revision of the BASN chip, we would like to complete the
layout now. We anticipate leaving a week for documentation and preparation for the final report
and presentation.
Oct 2010
ID
Task Name
Start
Finish
Nov 2010
Duration
10/17 10/24 10/31
1
Phase I
10/13/2010
10/29/2010
2.6w
2
Phase II
10/29/2010
11/5/2010
1.1w
3
Phase III
11/5/2010
11/19/2010
2.2w
4
Phase IV
11/22/2010
11/30/2010
1.4w
11/7
11/14 11/21
TASK BREAKDOWN
The first task is to complete all of the individual blocks. Aatmesh will complete the frequency to
voltage converter, error amplifier, VCO, and the PTAT. Alicia will complete the ADC, DAC, and
verify that the two work properly together with the register block.
Once the individual blocks have been completed, both team members will work on putting the
blocks together and simulating the entire system using a testbench.
Finally, the layout will need to be planned and implemented, and we will complete the final
project report and presentation together.
REFERENCES
[1] F.A. Farag, M.C. Schneider and C. Galup-Montoro, “A Fully Balanced Programmable
Sample-Hold Amplifier for Low-Voltage Applications”, ISCAS 2000, pp. 443-446, May 2000.
[2] Abdelouhab Dejoumai et al, “A new frequency locked-loop CMOS frequency to voltage
converter: Design and implementation” IEEE transactions on circuits and system 2001.
[3] Mohammad Danaie et al, “A Low-Voltage High-PSRR CMOS PTAT & Constant-Gm
Reference Circuit” 48th Midwest Symposium on Circuits and System.
[4] James L. McCreary and Paul R. Gray, “All-MOS Charge Redistribution Analog-to-Digital
Conversion Techniques—Part I”, IEEE Journal of Solid-State Circuits, vol. SC-10, no. 6,
December 1975.
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[5] Yeknami, Ali Fazli, Qazi, Fahad ; Dabrowski, Jerzy J. and Alvandpour, Atila , “Design of
OTAs for ultra-low-power sigma-delta ADCs in medical applications”, ICSES 2010, pp. 229-232,
September 2010.
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SIMULATION RESULTS
Figure 1: Bode plot of error amplifier as a function of the frequency
Figure 2: Initial state of VCO
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Figure 3: Steady state output of VCO
Figure 4: The transient results of the frequency-locked loop.
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Figure 5: Sample-hold circuit with source-follower buffer used for ADC [1].
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