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ECE 6332: Design Review 2
Aatmesh Shrivastava and Alicia Klinefelter
A Stable System Clock Generator Using Reference Clock Sampling
Abstract: In this project we would carry out the design of an on-chip accurate system
clock using a frequency locked loop. The proposed design would use an off-chip crystal
oscillator as its reference clock which can be turned off once the FLL is locked to the
reference frequency. The proposed scheme would save power that gets dissipated in
the generation of the clock by an order of magnitude. We would also implement a
temperature compensating scheme which would not allow the frequency of the clock to
drift.
PTAT
Clock coming
from crystal or
RF source
Save state in
event of source
powering off
F to V
Converter
_
Error Amp.
ADC
Register
Block
DAC
VCO
+
F to V
Converter
out
Figure 1: System Block Diagram
PROGRESS
F to V Converter:
A frequency to voltage converter, or FVC [4], is used to generate a voltage corresponding to a
frequency of oscillation. The higher the frequency, the lower the output voltage will be and so
the FVC can be viewed as an inverting amplifier.
The design is incorporated using a switching current source and switched capacitor scheme.
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Figure 2: Frequency to Voltage converter circuit
Amplifier
A very high gain operational amplifier is required. This would make sure the generated
frequency is same as the reference frequency signal.
The error amplifier is a folded cascade operational amplifier with source follower at the final
stage. The target gain for this amplifier is 100dB and phase margin is 80 degrees.
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Figure 3: Operational Amplifier Circuit
ADC:
Through searching for low-power, low-cost and accurate (high resolution) implementations of
ADCs, many used the sigma delta architecture as seen in Figure 1. Many alternative
implementations rely on resistor networks that can be too inaccurate for our application. This
architecture relies on over-sampling and noise shaping to compute the final output. The sigma
delta modulator produces an output signal, y[t], that is pulse-density modulated, or the density of
the output pulses imply what the input signal magnitude is.
x(t)
-
+
y[t]
+
Diff. Amp.
Comparator
DAC
Figure 4: Sigma-Delta Modulator
ADCs can either be oversampling or they can be Nyquist-rate converters (fs can only be as low
as the Nyquist criterion allows). By oversampling, much higher resolution can be achieved since
there is no longer a 1-to-1 relation between input and output samples. By oversampling, the bits
at the output y[t] can be averaged using a digital low-pass filter. The sigma-delta ADC allows for
oversampling to get a more accurate output signal, but can also operate as a Nyquist-rate
converter.
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For the ADC the differential amplifier, integrator, and comparator have been completed. The
DAC is still being completed but close to being done. Since we have a goal in mind for power
consumption, we are attempting to meet that.
The DAC design for the ADC is discussed below.
DAC:
The DAC will be used as part of the feedback loop in the ADC as well as a standalone block to
complete the digital-to-analog conversion from the register block. There are both voltage and
current steering DAC architectures that tend to be used. Voltage scaling networks can require
large capacitances or resistances and fail to be accurate. The current steering network seen in
Figure 2 is a 10-bit DAC with a series of scaled branches branches. Each branch’s current is 2x
the previous branch so that it is a network of scaled currents [1].
Figure 5: Current Steering/Scaling Network.
The thermometer decoder (seen as block in top left of Figure 2) for the most significant bits is
used to reduce glitching. Thermometer coding only has a 1-bit change from one input change to
the next, so this allows for a more stable output voltage. More of the MSB bits can be decoded
for accuracy, but this occurs at the cost of more transistors and larger area. This scaled current
value can then go into a current to voltage converter/amplifier to get a voltage proportional to
the input current coming from the current scaling network. The feedback resistor can be used
for scaling of the final output voltage. We have a high-gain op-amp in place for the circuit, and
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since it can become saturated at any current > 100nA, the goal is to get the output of the current
steering network as low as possible without losing accuracy.
VCO:
The voltage controlled oscillator is a ring oscillator based architecture where amplifier output
controls the frequency of oscillation. The higher the voltage, the higher the frequency of
oscillation will be. Figure 6 contains the delay element in the VCO and five such elements are
used in the VCO.
Figure 6: Delay element in a VCO element.
PTAT:
A PTAT provides a current that increases with temperature.
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In our design we have a VCO that gives a frequency output corresponding to an input voltage.
The drive of the MOS device decreases with temperature so in order to compensate for this
effect we will add a PTAT current to the ADC’s output which will give a constant current over a
wide range of temperatures. This will help in controlling the drift. The design of PTAT is work in
progress.
REMAINING TASKS
Once the current for the DAC is reduced as to not saturate the op-amp, the DAC’s resistor
network (R and 2R) values will need to be tweaked for absolute accuracy during conversion.
The DAC is part of the feedback loop for the ADC, so once it is completed it will be added to the
current ADC schematic and tested with the rest of the network. At this point some parameters
such as gain of the op-amps, resistor values, and capacitance (for the integrator) will be
modified slightly to get the correct output. Finally, the ADC and DAC will be tested together.
Similarly, once the DAC is completed the PTAT block can be designed. Finally, we will connect
all of the blocks together.
Questions to address when it comes to ADC/DAC design will include:

Assuming a low-pass filter is required at the output of the DAC, will an IIR be stable for
the bandwidth required?

What is the delay from the input of the ADC to the output of the DAC? This will help
determine how long the reference clock must remain on before it can be turned off.
ADDITIONAL SOURCES
[1] Brandon Greenley, Raymond Veith, Dong-Young Change, and Un-Ku Moon, “A LowVoltage 10-Bit CMOS DAC in 0.01-mm2 Die Area”, IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 52, no.5, pp. 246-250, May 2005.
A low-power current steering network is presented for a 10-bit DAC. The design uses a
thermometer decoder to decode the three MSB bits for increased accuracy. It also
discusses the tradeoffs between using more bits for the decoder and the area increase
due to the extra transistors. A linear current mirror is implemented along with a
suggested centroid layout technique for the final circuit.
[2] Li Yani, Yang Yingtang, Zhu Zhangming, “A novel low-voltage low-power bulk-driven
cascade current mirror”, ICACTE 2010, pp. 78-83, September 2010.
A new low-power technique for a current mirror is presented. The paper also compares
different, classic current mirror schematics and discusses how a cascade current mirror
will provide more drive for the output as well as a more accurate output current. The
performance of their presented current mirror is also more resistant to noise compared
to similar type circuits.
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Figure 7: Thermometer decoder circuit
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Figure 8: Thermometer decoder simulation results. Top three signals are the inputs signals (in0-in2) and the bottom seven are the
output signals (out0-out6).
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Figure 9: Integrator circuit with feedback resistor to allow for DC operation.
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Figure 10: Integrator output. Sawtooth output waveform in response to pulse input waveform.
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Figure 11: Scaled currents in each branch of the current steering network when all bits are asserted (every branch is enabled).
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Figure 12: The output of the frequency to voltage converter. It can be seen that the voltage settles after the frequency has been
stable.
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Figure 13: Bode plot of error amplifier as a function of the frequency at a common mode of 550mV, which is the DC output of the
FtoV converter at 200kHz clock.
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Figure 14: The transient results of the frequency-locked loop in the final DC operation the FtoV output of VCO and reference clock is
settling to the same voltage indicating that the frequency obtained through VCO is equal to the reference frequency.
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