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AFOSR/AFRL Center of Excellence:
The Science of Electronics in Extreme
Electromagnetic Environments
MOSFET Defect Enhanced Vulnerability to Terminal
Voltage Stress: A DFT and FEM Based Analysis
Chris Darmody, Dev Ettisserry and Neil Goldsman
Department of Electrical and Computer Engineering
University of Maryland College Park
Overview
•
•
•
•
Introduction: nano-MOSFETs and Vulnerability
Dielectric Breakdown and Tunneling Analysis with FEM
Role of Oxide Defects in EMI Vulnerability
Atomic Level Modeling of Defects & High Gate Voltage:
• Density Functional Theory (DFT) plus related modeling
tools.
• Model Agreement of MOS Oxide Charging with Exp.
• Summary and Future Work
1
Standard MOSFET (3D)
An Integrated Circuit can
contain a billion MOSFETs
Width ~ 50nm
Length
~ 20nm
SiO2
Thickness
~ 2 nm
2
Fermi Level: Relative
Position vs. Bias
MOS System
3
Printed Circuit Board (PCB)
Contains chips and metal lines
EMI can induce voltage variations on PCB traces that make their
way to device terminals causing unexpected potential differentials
on micro and nano device contacts.
4
FinFETs and Materials:
New FinFET vs. Old Standard MOSFET
VG
VS
VD
Gate Oxide
-------Channel
N-Drain
N-Source
P-Substrate
Wafer Thick
New FinFET Vertical
Design; Stands up like
a fin.
Old Bulk Design
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FinFET Design and
Advantages
Intel Corp.
• Design:
– High-k gate dielectric for thin
equivalent oxide thicknesses (sub
2nm)
– Thin SiO2 layer at interface between
high-k dielectric and substrate (1nm)
– Rounded corners reduce premature
inversion
• Advantages:
– Density scaling beyond planar
devices (sub 20nm)
– Large effective channel width
– Lower threshold and source-drain
leakage (fully depleted channel)
[1]
HfO2
SiO2
p-Si
[1] Wu et al, High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme (2010)
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Dielectric Defects and Breakdown in
V
FinFETs
G
• Oxide imperfections from
processing
• Variations of oxide
thickness
• Carrier tunneling breaks
weak oxide bonds which
form conducting paths
Gate Metal
IG
Direct
Tunneling
Leakage
tox
Oxide
Non-uniformity
Si Fin
Defects/Traps
IG
Trap-assisted
Tunneling
Leakage
Breakdown
through defect
paths
Saraswat, Thin Dielectrics for MOS Gate
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FinFET Vulnerabilities
• High-k dielectrics more trap-rich,
degrading device performance
• Gate voltage stresses cause trap
generation
• Soft breakdown: weak conduction
through single-trap path
• Progressive breakdown: trap
assisted tunneling
• Hard breakdown: critical trap
concentration and/or critical electric
field
• Less robust to oxide degradation
than lateral MOSFETs
IG [A]
• Traps increase gate leakage
Hard
Breakdown
Soft Breakdown
Progressive
Breakdown
Breakdown curve of SiO2/HfO2 gate dielectric layer
Fenfen et. al, TDDB characteristic and breakdown
mechanism of ultra-thin SiO2/HfO2 bilayer gate dielectrics
(2014)
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Analyzing Dielectric Reliability from
EMI in FinFETs
• Solve Poisson equation in
fin using the Finite Element
Method (FEM)
• Obtain values for:
EMI
IG
VG
– Potential (ϕ)
– Electric field (𝐸)
– Electron concentration (n)
– Hole concentration (p)
everywhere inside fin for
applied gate biases
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Solving Poisson Equation with FEM
𝛻 ∙ 𝜺𝒓 𝛻𝝓 =
𝑞
𝑞𝝓
−𝑞𝝓
+
(𝒏𝟎 𝑒𝑥𝑝
− 𝒏𝟎 𝑒𝑥𝑝
+ 𝑵−
𝑨 − 𝑵𝑫 )
𝜀0
𝑘𝑇
𝑘𝑇
n
•
p
dopant ions
Replace PDE with linear system of coupled
equations on discrete mesh
− Solve matrix equation
− Finer mesh near important regions
− Interpolate with piecewise-continuous
polynomials
•
Advantages of FEM over Finite Difference:
− Able to handle complicated geometries +
boundaries easily
− Error estimates and convergence rates wrt.
element size
− Automatically enforces jump conditions at
internal interfaces
− Formulation ensures discrete solution is the
best approximation to real solution wrt.
energy norm
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Voltage in Fin (SiO2)
Volts
VG=1V
VB=0V
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Electric Field at Interface (SiO2)
SiO2
Si
Post Processing
Electric Fields
E Field Scale:
3.2
MV
cm
Smallest Triangles:
0.3nm edges
12
Carrier Concentrations in Fin (SiO2)
cm-3
cm-3
13
Gate Current Tunneling
• Thin gate oxides:
– High electric fields
– Direct tunneling
currents
– Barrier for tunneling
(CB offset) smaller for
HfO2 than SiO2
– Trap-assisted tunneling
currents
Gate Metal
IG
Direct
Tunneling
Leakage
tox
Oxide
Non-uniformity
Si Fin
Defects/Traps
IG
Trap-assisted
Tunneling
Leakage
Saraswat, Thin Dielectrics for MOS Gate
14
WKB Tunneling
Tunneling, Dragica Vasileska and Gerhard Klimeck
Ox
Si
Ox
Si
Ox
Si
Ox
Si
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Gate Tunneling
Leakage Current
• Direct tunneling through trapezoidal oxide barrier at
low gate voltages/ thin oxides
• For Vg=1V in saturation:
– ID-on=661μA
– ID-off=nA range
– IG-tunnel=1.73μA
– IG/ID increases for
smaller devices
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Dielectric Breakdown
• Carrier tunneling can break weak oxide
bonds
Material
EBD
SiO2
10 MV/cm
• For tox=2nm, breakdown at VG=1.3V
HfO2
6 MV/cm
HfO2 Breakdown
SiO2 Breakdown
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Effect of Defects in FinFET Dielectric;
Analyze Reliability and EMI Effects with DFT
•
•
•
•
•
•
Fin thickness: Tfin=25nm
Oxide thickness:
Tox = 1.6nm
Height: Hfin=75nm
Fin Substrate: BOX =
Buried Oxide
Channel Length: Apprx.
14nm (not shown)
Rectangular geometry
contains corners.
Nowak, et al, IEEE Cir&Dev Mag, p20-31.
Jan/Feb 2004
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Investigate Role of Defects in EMI
•
Ideal Oxide
•
Oxide with Defect
Defects reduce performance and most likely enhance vulnerability
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Effect of Defects on MOSFETs; High Voltage
Bias Changes Threshold Voltage (Vt)
•
Positive shift in Vth following
HT positive bias stress due to
electron trapping.
•
Negative shift in Vth following
HT negative bias stress due to
hole trapping.
•
The degradation worsens over
time!
This work focuses on
NBTS degradation
potentially due to
OV hole traps
•
OV = Oxygen Vacancy
* Measurements by our collaborators at U.S. Army Research Lab,
Adelphi, MD.
20
Density Functional Theory: Use to Analyze
• Schrodinger wave equation that accounts for all the electrons and nuclei in
the system and their interactions.
2

Hˆ  
2me
Z I Z J e2
 Z I e2 1
e2
2 2 1

i   
   2      2M  I  2  
i , I ri  RI
i  j ri  r j
I
I  J RI  R J
I
2
i
Total wavefunction
• The kinetic and potential energies are altered by quantum effects like Pauli’s
exclusion – not quantifiable.
• DFT provides a tractable accurate solution for the ground state eigenvalues
(energy) and electron density.
– Replaces the complicated interacting system Hamiltonian by a sum of noninteracting Hamiltonians.
– Uses electron density (one function in space) as the fundamental property
instead of ψtot.
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DFT Shows Oxygen vacancy (OV) defects give
rise to charge trapping centers
Structural and
electronic properties
of OVs in MOS
oxide regions were
studied.
Structures of OV in oxide regions:
(1) Basic Low-energy Dimer,
(2) High-energy forward-projected (fp),
(3) High-energy back-projected (bp)
•
•
•
Upon hole capture, basic dimer spontaneously forms positive fp.
fp thermally transforms to bp.
Also, fp and bp are stable when neutral.
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Transient modeling of OV hole trap activation
under NBTS (contd..)
• The time-dependent total concentration of activated hole traps (positive
charges) is translated to voltage shift in negative direction.
• Δ𝑉 𝑡 = −
𝑞𝑁
6
𝑖=2 𝑥𝑖 (𝑡)
𝐶
Experimental
Simulated NBTS
OV hole trap activation is a serious contributor to HTGB reliability degradation in
4H-SiC MOSFETs (from integrated modeling using DFT and rate equations) .
[1] A. J. Lelis et. al, IEEE T-ED, vol. 62, no.2, pp.316-323, 2015.
[2] M.A. Anders et.al., IIRW pp. 16-19, Oct. 2014.
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Summary and Future
•
EMI can couple to micro and nano devices via PC Board traces.
•
MOS Gate Oxides are especially vulnerable to induced terminal voltages.
•
Created FEM solver for nonlinear Poisson equation in FinFET
•
Calculated Dielectric Breakdown Voltages and Tunneling Effects with Solver.
•
Oxides are very thin and can have defects (Oxygen Vacancies) which enhance
vulnerability
•
Density Functional Theory plus related modeling tools calculates defect states on
atomic level.
•
Transient Arrhenius type model developed that uses DFT QM Atomic Structure
and State results to quantify charging.
•
Model correctly quantifies MOSFET threshold voltage shift due to gate voltage
bias stress.
•
Future:
•
Add transient analysis to oxide field calculations
•
Investigate defects in HfO2 (new high K) gate dielectrics (Current work was
SiO2)
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