Download Circuit Design Issues in Multi

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Class Presentation for VLSI Course
Major Reference is:
Circuit Design Issues in Multi-Gate FET
CMOS Technologies
Christian Pacha, Klaus VonArnim, Thomas Schulz, Wade Xiong, Michael Gostkowski,
Gerhard Knoblinger, Andrew Marshal, Thomas Nirschl, Joerg Berthold, Christian Russ,
Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer
In ISSCC2006/ SESSION 23/ TECHNOLOGY AND ARCHITECTURE DIRECTIONS/ 23.2
Instructor: S. M. Fakhraee
Presented by: Behzad Ebrahimi
December 2006
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Outline
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Introduction
Comparison speed in different structures
Low power design
Opamp with FinFET
I/O and ESD protection
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Introduction
•
•
Superior Control of the Channel
•
Reduced Short Channel
Effect
•
Lower Leakage Current
Better Cicuit Performance
•
Novel Gate-Stack materials
•
Reduced parasitic
capacitances
•
Hole mobility improvement
Multiple-Gate FET Transistors are
promising device structures for
sub-45nm technology.
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Multi-Gate FET
WFIN
L
HFIN
WEFF  2HFIN  WFIN
WEFF  2HFIN
TriGate
Double Gate/ FinFET
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Multi-Gate FET
Fabrication of tall Triple-Gate
FETs with 10nm fin with
demonstrates the long-term
scalability.

Relaxed FinFET and TripleGate device dimensions were
chosen to increase yield and
homogeneity.
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Triple-Gate Control allows for higher
device currents and relaxed process
requirements.
From [1]
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Multi-Fin MuGFET
DRAIN
DRAIN
N+
Wfin
50nm
MDR
200
nm
POLY
Lg
Lg
GATE
pitch
LgLg
GATE
500nm
WEFF  2nH FIN
500nm
POLY
FinFET:
Wgeo
Wgeo
SCGS
N+
SOURCE
SOURCE
WEFF  n(2H FIN  WFIN )
Triple-Gate FET:
WFP  np FIN
Footprint:
Area gain over bulk CMOS: W
EFF
np FIN
1
Three-dimensional device topology in
combination with a small fin pitch
improves the circuit density.
From [1]
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Multi-Fin MuGFET
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The discrete transistor widths of multi-fin MUGFETs are a circuit
design limitation compared to bulk CMOS.
This design limitation is not critical for nFET/pFET sizing in CMOS
logic circuits, especially for a <110> channel surface orientation [1]
Discrete transistor widths are a concern for SRAM cells which are
composed of single-fin devices.
In SRAM the drive currents of single-fin MUGFETs can be modified
only by different gate lengths.
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Speed in Different Structure
• Performance, active and leakage
current of these structures are
measured using 24 ring oscillator (RO)
modules.
• The ROs are composed of various
gates up to NAND3/NOR3 complexity
with a fan out two (FO2) .
Triple-Gate circuits using TiN metal gate
electrodes are 65% faster than FinFET
circuits with poly-Si gate electrodes at
VDD=1.2V.
From [1]
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Low Power Design
• Low power circuits require additional
high-VT devices to implement noncritical paths to switch-off non-active
circuit blocks.
• Fast circuit are based on devices
with minimum gate length while
leakage sensetive circuits are made of
devices with longer gate lengths but
smaller off-currents.
From [1]
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Operational Amplifier
25
20
10*R
[dB]
15
10
A
• Due to the large multi-fin transistors
with non-minimum gate lengths, the
effect of discrete device widths on
circuit design is negligible.
• Bode plot ( gain vs. frequency)
configured as a 20dB inverting
amplifier.
• The low-frequency open loop gain is
A0=45dB . This is comparable with
typical open loop gains achievable in
deep sub-micron planar CMOS
technologies.
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R
Vout
0
Vin
Vcm
Vcm
VDD=1.5V
-5
-10
1.0E+01
1.0E+02
1.0E+03
1.0E+04
Frequenz
1.0E+05
1.0E+06
1.0E+07
[Hz]
From [3]
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I/O & ESD
 MuGFETs show a low ESD current
capability and high ESD sensitivity.
 This motivates the co-integration of
more robust PD-SOI devices for ESD
clamps and multi-fin MuGFETs to
provide large currents for fast I/O
drivers.
From [1]
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Conclusion
• Three-dimensional device topology in combination with a
small fin pitch in multifin MuGFET improves the circuit
density
• Novel Gate-Stack materials can improve performance.
• The use of FinFET in low power applications is
considered.
• The successful design and realization of the most
important analog circuits (Miler op-amp) in a MuGFET
technology is presented for the first time.
• We see a solution to the electrostatic discharge (ESD)
sensitivity of MuGFETs.
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THANKS FOR YOUR
ATTENTION
ANY QUESTION?
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References:
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1. C. Pacha et al., “Circuit Design Issues in Multi-Gate FET CMOS
Technologies,” ISSCC Dig. Tech Papers, pp. 420-421, February ., 2006
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2. N. Collaert et-al, “A Functional 41-Stage Ring Oscillator Using Scaled
FinFET Devuces WIth 25-nm Gate Lengths and 10-nm Fin Widths
Applicable for the 45-nm CMOS Node”, IEEE Electron Device Letters, Vol
25, No 8, August 2004, p568-570
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3. G. Knoblinger et.al., “Design and Evaluation of Basic Analog Circuit in
an Emerging MuGFET Technology”, IEEE SOI Conference, Oct 4-6, 2005
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4. C.Russ et al., “ ESD Evaluation of the Emerging MuGFET Technology,”
EOS/ESD Symp., pp, 280-289, Sept., 2005
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