Download 17-1 Air Spacers to Reduce Capacitance in 10nm FinFETs

Air Spacers to Reduce Capacitance in 10nm FinFETs: Parasitic capacitance slows down the switching
of transistors with closely packed features, such as the tightly packed gate and contacts in a FinFET. Lowk dielectrics, or insulators, are used to counter it, but as devices scale smaller and dielectrics get thinner
the capacitance continues to increase. Air is considered to be the perfect insulator but nanoscale air
spacers, or voids, are difficult to fabricate. They must be very narrow, quite deep, and yet precisely
uniform. While FinFET air spacers have been demonstrated, researchers from IBM and Globalfoundries
will report the first air spacers at the 10nm FinFET node. These reduced capacitance at the transistor level
by as much as 25%, and in a ring oscillator test circuit by as much as 15%. The researchers say a partial
air spacer scheme represents a good way to introduce air spacers at this scale because it minimizes
damage to the FinFET, as does the high-selectivity etching process used to fabricate them.
Top left: TEM image of a FinFET transistor with air spacers (the white spaces) at 10nm dimensions.
Top right: Damage after an aggressive spacer pulldown process; specifically, erosion of the fin and
source/drain epitaxy.
Below the images: Schematic of a partial air spacer structure. Air spacers are formed only above the fin
top to minimize the impact on the gate stack. Dielectric liners are used to further protect gate stacks
during air spacer fabrication processes.
(Paper #17.1, “Air Spacer for 10nm FinFET CMOS and Beyond,” K. Cheng et al, IBM/Globalfoundries)