Download Gate dielectric breakdown Silicon avalanche

MOSFET Defect Enhanced Vulnerability to
Terminal Voltage Stress: A DFT, FD and Lumped
Element Based Analysis
Neil Goldsman
Chris Darmody, Yumeng Cui, Dev Ettisserry
Acknowledgement: This work is supported by AFOSR/AFRL COE
Grant #FA9550-15-1-0171
Date: 23 March 2017
1/23
Outline Of Presentation
• Motivation
– New Nano Transistors Vulnerable to EMI
• Objective
– Quantify and Predict Vulnerability from EMI on Achieve on
Macroscopic and Nanoscopic Levels
• Theoretical Basis:
– Oxide and Thermal Related Breakdown and Disruption
• Methodology:
– Atomic level, Distributed and Lumped Modeling
• Results
• Conclusions
• Future Work
2/23
Motivation: NanoMOSFET Vulnerability
1. Nano-Size MOSFETs fundamental building block
most electronics (especially FinFETs)
2. Key Device Components are extremely small
a. Gate Dielectrics: 2nm
b. Channel Length 15nm
3. Standard terminal voltage differential levels: 1Volt
4. EMI may cause much higher voltage potential
differences.
1. Gate dielectric breakdown
2. Silicon avalanche breakdown
3. Silicon thermal damage
State of art Nano
MOSFET: FinFET
3/23
Objectives:
1.
2.
3.
Quantify and Predict Vulnerability from EMI
Achieve on Macroscopic and Nanoscopic Levels
Use mainly a variety of computer modeling methods
Explain and Develop Methodologies for the Three Major Mechanisms of
Nano-Scale MOSFETs (Mainly FinFETs) EMI Related Damage and
Disruption.
1. Gate dielectric breakdown
2. Silicon avalanche breakdown
3. Silicon thermal damage
4/23
Gate Dielectric Defects and
Breakdown in FinFETs
• Oxide imperfections from processing
• Variations of oxide thickness
• Carrier tunneling breaks weak oxide bonds
which form conducting paths
Breakdown
through defect
paths
Saraswat, Thin Dielectrics for MOS Gate
7
5/23
Density Functional Theory: Use to Analyze
• Schrodinger wave equation that accounts for all the electrons and nuclei in the system and their
interactions.
2

ˆ 
H
2me

i
2
i

i,I
Z I Z J e2
 Z I e2
1
e2
2
1
2
I   
   

 

2
2
M
2
ri  RI
i  j ri  r j
I
I  J RI  R J
I
Total wavefunction
• The kinetic and potential energies are altered by quantum effects like Pauli’s exclusion – not
quantifiable.
• DFT provides a tractable accurate solution for the ground state eigenvalues (energy) and electron
density.
– Replaces the complicated interacting system Hamiltonian by a sum of non-interacting
Hamiltonians.
– Uses electron density (one function in space) as the fundamental property instead of ψtot.
6/23
Si-SiO2 DFT Supercell:
FinFET Gate Inteface
Amorphous SiO2
Defected Interface
Region
Si-Si Bond
Oxygen Vacancy
SiO2
Si
Si Crystal Bulk
Perform DFT to get minimum
energy atomic structure
Interface
7/23
Extract Atomic Perturbation Potential on MOSFET
Gate Si/SiO2 Interface
Silicon
Oxygen
1. Atomic Potential Interface Plane is quantified.
2. Use this atomic potential to quantify defects and how they can lead to
breakdown.
8/23
Isosurface Plot of Electron Density
Stretched Si-Si bond (250pm vs 235pm):
Lowered electron density in bond shows
point of weakness at oxide interface
SiO2
Electron density is highest
where bonds are expected
Si
9/23
Silicon-Oxygen Bond Analysis
Oxygen
Critical Point rc
−0.19
𝜌(𝑟𝑐 )
1.46
𝑟
= Avg. Bond Length [Å]
Bond Path
Silicon
r
c Oxygen
Silicon
Electron density along bond path
Electron density gradient (𝛻𝜌)
streamlines showing Si-O bond path
10/23
Semiconductor Device Modeling
Access Internal Macroscopic Device Characteristics by Solving
Semiconductor Equations Numerically
5 Semiconductor Equations:
Poisson
Electron Continuity
Hole Continuity
Electron Current
Hole Current
Solution Gives 5 State
Variables of FinFET:
• Φ(x,y)
• n(x,y), p(x,y),
• Jn(x,), Jp(x,y)
11/23
FinFET: Solution to Semiconductor Equations provides internal characteristics:
Potential, Carrier Concentrations, Currents Densities
x
VGS = 1.2 V
VDS = 1.2 V
Wch = 15 nm
tox = 3 nm
Lch = 25 nm
NA = 4e18 cm-3
ND = 1e20 cm-3
D
+VA
tox
ND
y
Lch
+VG
G
NA
+VG
G
ND
Oxide
S
Channel
12
12/23
FinFET: Gate Cross
Section
gate
p body
W = 10 nm
tox = 1.3 nm
H = 25 nm
Buried oxide
tbox = 100 nm
VG = 1.2 V
VDS = 0 V
13
13/23
x
D
+VA
tox
ND
y
+VG
G
NA
Lch
+VG
FinFET:
Calculated Current density
G
ND
Oxide
S
Channel
Source
Current is concentrated
close to channel, 100time difference.
Surface depletion width
~ 5 nm
tox ↓ -> better control
Drain
14
14/23
Transient device-level simulation
using mixed-level simulator
x
Drain
tox
Input to FinFET
Lch
+VG
NA~1018cm-3
+VG
Gate
Gate
ND~1020 cm-3
Oxide
Source
Low Power
+VD
ND~1020 cm-3
y
High Power
Channel
Periodic pulse voltage applied on gate.
Period T = 5 ns, Pulse width W = 1ns
V1 = 1.2 V, V2 = 2.0 V, VDS = 1.2 V
Change in drain current exactly follows change in
voltage. (Rising/falling edge TR = TF = 20 ps)
VG = V1 = 1.2 V
VG = V2 = 2.0 V
Drain current ID
8.632 𝜇𝐴
46.12 𝜇𝐴
Electrical power ID . VDS
10.36 𝜇𝑊
55.35 𝜇𝑊
15/23
Avalanche Multiplication and Breakdown
Additional carriers (electron and hole
pairs) are added into conducting
bands, due to impact ionization,
described by continuity equation
For electrons in silicon,
𝜕𝑛
1
=0=−
𝛻 ∙ 𝐽𝑛 + 𝐺𝐴
𝜕𝑡
−𝑞
Generation due to avalanche
multiplication
ℰ𝐼 = 3.6 eV: Effective ionization
threshold energy;
𝐸𝑇 , 𝐸𝑃 , 𝐸𝐼 : Threshold field for thermal,
optical phonon, and ionization
scattering, respectively.
1
𝛼𝑛 𝐽𝑛 +𝛼𝑝 𝐽𝑝
𝑞
where 𝛼𝑛 and 𝛼𝑝 are electron and
hole ionization rates, respectively.
𝐺𝐴 =
𝛼𝑛 = 𝛼𝑛 𝐸 =
Sim. Case
−𝐸𝐼
𝑞𝐸 𝐸 1+𝐸 𝐸 +𝐸𝑇
𝑃
𝑒
Input to FinFET
ℰ𝐼
Low Power
(VG = V1)
High Power
(VG = V2)
Low
Temp.
High
Temp.
w/ Aval.
43.69 𝜇𝑊
95.17 𝜇𝑊
376.2 K
441.9 K
w/o Aval.
10.36 𝜇𝑊
55.35 𝜇𝑊
322.7 K
384.5 K
16/23
Thermal (heat transfer)
simulation with 3D
structure
Each red circuit symbol
stands for a thermal
resistor, totaling 15
with some hidden due
to the view angle.
Capacitors are not
shown and are added
in the circuit for each
conducting block.
17/23
Thermal (heat transfer) simulation
with 2D structure (distributed)
2-D Heat transfer equation
𝜕
𝜌𝐶𝑃 𝑇 𝑥, 𝑦, 𝑡 + 𝐾𝛻 2 𝑇 𝑥, 𝑦, 𝑡 = 𝑄 𝑥, 𝑦, 𝑡
𝜕𝑡
Gate
tox = 3 nm
Channel
Field
Oxide
Body
Wch = 10 nm
G
O
X
HFin = 25 nm
HBOX = 80 nm
𝜌: Density
𝐶𝑃 : Specific heat
K: Thermal conductivity
• Heat source Q is
uniformly added in
the channel region
(V x I)
• Heat sink (T = 300
K) is applied as
boundary condition
far (100 nm) away
from the channel
region.
18/23
Thermal (heat transfer)
simulation with 2D structure
(distributed)
Spatial dependence near steady state (t ≲ 6 𝑛𝑠)
2-D Heat transfer equation
𝜕
𝜌𝐶𝑃 𝑇 𝑥, 𝑦, 𝑡 + 𝐾𝛻 2 𝑇 𝑥, 𝑦, 𝑡 = 𝑄 𝑥, 𝑦, 𝑡
𝜕𝑡
Channel Oxide
Thermal Power
In Channel
Max Temp.
405.3 K
365.6 K
55.35 𝜇𝑊
Min Temp.
320.7 K
313.0 K
10.36 𝜇𝑊
Temperature is averaged within the entire
region of the oxide and channel, respectively,
and recorded with time.
(Tamb = 300 K)
19/23
Thermal (heat transfer) simulation
with 3D structure (lumped)
Gate
Channel
Gate Oxide
Drain
Field Oxide
3-D equivalent circuit:
• Totaling 15 resistors, 10 capacitors
• Channel is broken into 7 parts (6R+1C)
to improve accuracy, others are treated
as 1 pair lumped element (1R+1C) based
on geometry characteristics.
Source
Body
20/23
Thermal (heat transfer) simulation
with 3D structure (lumped)
Voltage Input to
FinFET
Channel Temperature
(Tamb = 300 K)
Oxide Temperature
Thermal Power
In Channel
1x
power
5x
power
10x
power
1x
power
5x
power
10x
power
1x
power
High Temp.
384.5 K
602.7 K
1814 K
379.0 K
582.2 K
1716 K
55.35 𝜇𝑊
Low Temp.
322.7 K
462.6 K
1113 K
321.2 K
452.1 K
1062 K
10.36 𝜇𝑊
21/23
Conclusions
•
•
•
•
•
•
•
•
EMI can couple to micro and nano devices via PC Board traces.
MOS nm Gate Oxides are especially vulnerable to induced terminal voltages.
FinFET channels vulnerable to avalanche breakdown and thermal damage
Calculated Dielectric Breakdown Voltages and Tunneling Effects with Solver.
Density Functional Theory (DFT) calculates potential atomic level (microscopic quantities).
DFT Identifies weak atomic bonds at Si-SiO2 Interface, potential vulnerable locations.
Induced Voltages of only 2 Volts can destroy critical feature of Nano-MOSFET (Gate Dielectric)
Induced MOSFET Source- Drain Voltages of 5 Volts can give rise to avalanche breakdown:
• Temporary Disruptions
• Induced MOSFET Source-Drain Voltage of 5 Volts or more leads to Joule heating that can damage
device.
24
22/23
Future
• Continue DFT effort to identify weak atomic bonds in dielectric and interface and quantify energy
needed to break bonds and damage device.
• Perform more semiconductor device simulations by solving semiconductor equations for Nano
MOSFET (FinFET)
• Simulations give internal macroscopic device state variables versus location (n(x,y), J(x,y),
E(x,y0, etc.
• Use internal variables as input to DFT and Thermal calculations to quantify
• Effect of weak atomic bonds and potential atomic lattice damage
• Effect of high temperatures resulting from Joule heating
• Include nonlinear avalanche effects in Joule heating
• Assess how avalanche breakdown can cause circuit malfunction
• Compare results with experimental data, either from literature or from test chips that we design
in-house and send out for fabrication to foundry services (MOSIS, for example).
23/23