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Matakuliah Tahun Versi : H0362/Very Large Scale Integrated Circuits : 2005 : versi/01 Pertemuan 13 Memory 1 Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menerapkan gerbang logik, switching logik, dan atau struktur deskripsi Verilog untuk membangun sistem memory sederhana dalam CMOS VLSI. 2 Static Memory World line wl MAR MAL bit bit General SRAM cell wl VDD wl VDD MAL MAL bit bit MAR bit 6T cell CMOS SRAM circuit MAR bit 4T cell CMOS SRAM with poly resistor 3 Static Memory Wl_1 bit_1 VDD bit_1 bit_2 bit_2 Wl_2 2 port CMOS SRAM cell 4 2 control address SRAM Arrays WE D0 D1 D2 En a0 a1 Nxn array data I/O Dn-3 Dn-2 Dn-1 am-2 am-1 wl bit Left core bit MUX Row driver Single cell Row (world line) decoder Row driver High level view SRAM Right core Column decoder Central SRAM block architecture MUX 5 SRAM Arrays dN-1 dN-1 d3 d3 d2 d2 d1 d1 d0 d0 WL_0 WL_1 WL_2 WL_3 WL_4 WL_5 Cell arrangement in a core region 6 SRAM Arrays Row decoder Address Latch A3 A2 A1 A0 Column decoder Am-1 Am-2 Column select (y) Row select (x) Basic Addressing Scheme 7 5 Precharge Data in Sense amp I/O WE En SRAM Arrays Data out 8 World line Dynamic RAMs WL + Mn Access FET Vpower - Storage capacitor Vs 1T DRAM cell WL=0 WL=1 Input Vd Write operation ON + Vs - OFF + Vs - Hold 9 Dynamic RAMs WL=0 IL Vmax + Vs Minimum logic 1 voltage V1 t - 0 th Charge leakage in a DRAM cell 10 ROM Arrays Read Only Memories (ROM) are used for permanent bit storage. The structure of a ROM array is similar to that used for RAMS. However, the data cannot be alltered once the chip is fabricated. Electrically programmable ROMs PROMs) allow the user to store data as required by the application. Special voltage settings are used to write to the cells. 11 RESUME • Static memory: static RAMs Arrays. • Dynamic RAMS. • ROM Arrays. 12
