Download 9T Low Swing SRAM

1
Design of a 1 GHz Low Swing 9T-SRAM Register File
with Decision Feedback Equalization
Rishi Gupta, Ming-Hung Kuo, Student Member, IEEE, Jarrod Jackson, Student Member, IEEE , and
Jon Guerber, Student Member, IEEE

Abstract—The design and simulation of a 1 GHz low swing 9TSRAM register file has been analyzed. This register file employs
Decision Feedback Equalization to greatly enhance the reading
speed. With the proposed structure, it eliminates the need to precharge the bit lines in traditional low swing SRAM devices. This
system has been simulated with a novel buffered sense amplifier
and has been run through process corners with pseudo-random
input codes. Comparisons will be made to traditional SRAM
devices and explanations of Decision Feedback Equalization
(DFE) will be given.
Index Terms—Current Steering,
Equalization, Register File, SRAM
Decision
Feedback
I. INTRODUCTION
T
II. SRAM REGISTER FILE SYSTEM LEVEL DESIGN
A. Top Level Architecture
An SRAM register file is typically designed with an array of
SRAM unit cells forming the register file array. These SRAM
Manuscript received March 19, 2009.
J. Guerber, R. Gupta, M. Kuo, and J. Jackson are with the Oregon State
University, Analog and Mixed Signal Department, Corvallis, OR 97330 USA
(e-mail:guerberj@ eecs.orst.edu).
B. Decoder Architecture
To determine which SRAM cell to use, a row and column
decoder is used to addresses each cell. Control logic is then
used to correctly route addresses and enable both reading and
writing when desired. Within the control logic block shown in
Figure 1, a PRBS generator is integrated to perform in-circuit
testing. The decoder architecture can be seen in Figure 2.
This decoder generates 16 outputs from a 4-bit binary input.
The output is delivered with a longer period than normal to
prevent discontinuities in the reading of SRAM cell words in
high throughput operation. These discontinuities are due to
the non-overlapping nature of the master clock and would
reduce overall device speed.
Data
Address
RE WE
Control
Logic
Bit Line Decoder
Word Line Decoder
he progress of civilization depends on the ability to
remember and make decisions based on past events. This
concept has not been lost with the transition to a computer
age, where nearly every useful algorithm exploits the storage
of massive quantities of previously computed data. This
necessitates long term and short term memories within
computing structures. One of the most popular short term
memory structures that can be built right onto a
microprocessor device is the SRAM cell.
While SRAM has been incorporated as fast and
integrateable memory of choice for years, it has often
dominated the leakage power and speed considerations of the
device, making its design non-trivial. With the scaling of
devices into the deep-submicron regime, redesigned lowpower high speed SRAM must be investigated.
In this paper, a low swing SRAM has been designed that
requires no bitline pre-charge and includes decision feedback
equalization to improve speed. This paper will be constructed
as follow: Section 2 will feature the system level design of the
SRAM register file, Section 3 will feature actual schematic
simulations and corner analysis, Section 4 will discuss the
basics of decision feedback equalization, and Section 5 will
draw some conclusions about the design and highlight future
work to be done of the system.
devices will each hold 1 bit of information and have modes for
both reading and writing. When reading, the content of each
SRAM cell will go to a bitline upon a word line selection. The
selected cell is then drive the bit line either high (to Vdd) or
low (to Gnd) depending the stored data in the cell. These bit
lines are fed into sense amplifiers as shown in Figure 1. The
sense amplifier will detect which line is higher in voltage after
a period of time and decode whether a 1 or 0 was originally
present in the cell. Once this number has been found, it is
passed to an output latch and then used in other circuit
computations.
Register File Array
Sense Amplifier Block
Output Buffer
Figure 1: Top Level SRAM Register File Architecture
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BL1 BL2
OUT1
OUT2
BL2
BL1
WL1
OUT3
OUT4
M1
M3
OUT5
M5
OUT6
M6
M2
M4
OUT7
OUT8
M7
M8
OUT9
OUT10
WL2
M9
OUT11
OUT12
Figure 3: 9-T SRAM Cell Design
OUT13
OUT14
OUT15
O
OUT16
O
A4 A3 A4 A3 A4 A3 A4 A3 A2 A1 A2 A1 A2 A1 A2 A1
Figure 2: 16-bit Decoder with Overlapping Outputs
O
Q
M7
WL2
M8
Q
O
M9
DFE
C. SRAM Register File Architecture
The proposed SRAM unit cell is shown in Figure 3. This
cell features the traditional 6-T SRAM cell with two write
enabling transistors M5 and M6. The bottom NMOS M9
enable a reading operation by allowing current to flow through
M7 and M8 transistors in a direction decided by the bit
polarity contained in the cell. This current will determine the
voltage that feed to the sense amplifier shown in Figure 4.
Notice that there are separate bitlines for both reading and
writing, allowing for higher data access speed in the register
file. Feeding from the sense amplifier output is the decision
feedback equalizer, which improve the speed and power
consumption of the design by pulling up harder on bit line that
had been pulled down in the previous cycle. DFE will be
further discussed in the following sections.
While most conventional register file cells can read and
write concurrently contains 10 transistors as shown in Figure
7, the proposed design has only 9. In 10-T register file, only
one bitline at a time is pulled down and then reset before
comparison, requiring the input to each line to have both an
enable and data transistor. This can be reduced however with
a current steering approach where the bottom transistor enable
the current steering for a cell and 2 more transistors send data
to each bitline. This approach reduces chip area and allows
for faster speed data conversion due to no need to pre-charge
the bit lines.
Figure 4: SRAM Bit line with Sense Amplifier and Decision
Feedback Equalization
D. Sense Amplifier Architecture
A critical part of low power SRAM register files is the sense
amplifier. It is used to detect a change in the bitline during
read operations. This amplifier has to be fast enough to not
limit conversion speed (faster than 1 GHz), able to detect low
swing input (smaller then 100mV) and not disrupt the bitline
voltages during operation (high input impedance). To meet all
these requirements, the senses amplifier shown in Figure 5
was used.
This amplifier contains the traditional high speed clocked
latch core which can detect 50mV signals at speeds above 2
GHz. When tested this core worked well, but produced
excessive kickback noise, corrupting previous data for
decision feedback correction to work well. Thus a common
gate input buffer was added to buffer clock feedthrough and
provide additional input transconductance [3]. This sense
amplifier has over twice the sensitivity of the provided
standard cell amplifier in the cell library.
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BL1 BL2
OUT-
OUT+
IN+
IN-
M1
M3
M5
M6
M2
CLK
BL1
WL1
CLK
CLK
BL2
M4
CLK
WL2
M7
M8
M9
M10
CLK
Figure 5: High Resolution, Low Kickback Sense Amplifier
Figure 7: Conventional 10-T SRAM Bit cell
Figure 6: Conventional SRAM Register File Switching Characteristics
Figure 8: Proposed SRAM Register Filer Switching Characteristics
III. SIMULATION RESULTS AND SYSTEM COMPARISONS
This SRAM cell was designed and simulated in conjunction
with a 10-T register file whose unit cell is shown in Figure 7.
The switching results of this structure are shown in 6 for two
reads. Assuming a read were to occur every cycle, one can
read from the plot that there would be nearly 500 µA of
average current. Also, a read conversion takes at least twice
as long compare to the proposed solution due to the pre-charge
of the bitlines in the second phase of the clock.
The results of the proposed SRAM register file are shown in
Figure 8. In this simulation one SRAM cell is reading every
cycle, there is always a non-zero current flow. However, this
current is much lower than the conventional case and ends up
being around 25 µA. Additionally since there is no bit line
pre-charge needed, the reading can occur at least twice as fast
as in the conventional case.
One aspect of any high speed serial link circuit is the
examination of the bit error rate. Since there were no outright
errors in these simulations, an eye diagram was created to
examine the margin between read data points. An eye
diagram plotting constant reads under typical conditions with
and without DFE can be seen in Figure 9. Clearly, DFE opens
the eye allowing for low bit error rates and potentially higher
speeds. Figure 10 shows this same measurement with
different mismatch corner cases. The worst eye occurs at a
slow slow corner and the eye is still around 50 mV which is
detectable by the sense amplifier. Still to be done are corner
simulations with temperature mismatches.
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Figure 9: Eye Diagram for Typical reading with (Red) and without DFE (Blue)
Fast NMOS Fast PMOS Corner (90.08mV)
Fast NMOS Slow PMOS Corner (77.90 mV)
Slow NMOS Fast PMOS Corner (67.36 mV)
Slow NMOS Slow PMOS Corner (50.77mV)
Figure 10: Eye Diagrams for Corner Simulations with DFE
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Driver
Bitline 2
Voltage
Bitline 1
Time
= Without DFE
= With DFE
Figure 11: Time Domain DFE on an SRAM Serial Link
Figure 12: Block Diagram DFE Implementation and Placement in Serial Link System
IV. DECISION FEEDBACK EQUALIZATION
V. CONCLUSIONS AND FUTURE WORK
In most high speed serial links, the non-zero link
capacitance and resistance will cause residual charges to be
present from previous signals. These charges are commonly
referred to as inter-symbol interference and diminish over time
[1]. Ideally, if the line resistance and capacitance are known,
these interference charges can be approximated for each
previous read cycle.
Decision feedback equalization (DFE) can be used to
mitigate the effect of inter-symbol interference on the serial
link. In the case of the SRAM register file a read will pull
down the voltage on one of the two lines while pulling up the
other in proportion to the pull-down strength of the SRAM
and the pull-up strength of the line. If there is no read during
the next cycle, the SRAM will automatically reset both bit
lines to Vdd. However, if there is a read on the following
cycle, there will be some residual interference on the line and
the difference in line voltages will not be zero. With a
sufficiently fast clocking scheme, this initial difference will
cause bit errors. However, by switching in an extra pull up
resistor on the line that had previously gone low, as shown in
Figure 4, the bit lines can dynamically compensate for
previous interference. Figure 11illustrates the concept of time
domain decision feedback equalization.
Currently in this design, the DFE cancels only one previous
inter-symbol interference event, however more taps or
feedback paths could be added for cancelation of event further
in the past.
Figure 12 illustrates the multiple tap
implementations as well as the location of DFE in the
complete serial link.
This paper has proposed a 9-T SRAM Register file with
decision feedback equalization to reduce bit error rates. This
register file will operate at greater than 1 GHz with only 20µA
of current for one continuously reading unit cell.
While much work has been done on this design, future
improvements can be made such as increasing speed by
designing a faster test bench and adding more taps to the DFE.
The SRAM cell should also be optimized for area and
strengths while the DFE should be accurately tuned for the
maximum eye width.
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VI. REFERENCES
S. Haykin, “Communications Systems,” John Wiley Publishing, Fourth
Edition, 2001.
[2] Dr. Patrick Chiang Personnel Discussions.
[3] H. Chow, S. Chang, “High Performance Sense Amplifier Circuit for
Low Power SRAM Applications” ISCAS 2004
[4] J. Rabey et. al. “Digital Integrated Circuits,” Prentice-Hall Publishing,
Second Edition, 2003.
[1]
VII. AUTHORS
Rishi Gupta received the B.S. degree in Electrical Engineering from Oregon
State University in 2007 and is currently working toward a M.S degree in
Electrical Engineering from Oregon State University.
Ming-Hung Kuo (S’07) was born in Taiwan in 1985.
He received the B.S. degree in Electrical Engineering
from Oregon State University, Corvallis, Oregon,
USA in 2008 and is currently working toward a M.S
degree in Electrical Engineering from Oregon State
University.
His research interests include switched-capacitor
filter design and bandpass delta-sigma data
converters design.
Jarrod Jackson is a student at Oregon State
University, pursuing a Bachelor’s degree in Electrical
& Computer Engineering.
During the summer of 2008 he was at NASA
Langley Research Center contributing to the
algorithms of an intelligent adaptive optoelectronic
celestial navigation system for autonomous missions.
During 2007, he conducted research at the Pacific
Northwest National Laboratory’s Marine Science
Lab, deploying optoelectronic sensors to characterize
the underwater light field of a prototype fiber optic
lighting system.
Mr. Jackson is currently serving as the President of the student chapter of
IEEE at Oregon State University.
Jon Guerber (S’05) was born in Clackamas, Oregon,
USA in 1986. He received the B.S. degree in
Electrical Engineering from Oregon State University
in 2008 and is currently working towards a Masters in
Electrical Engineering from Oregon State University.
During the summer of 2008 he was with Teradyne
Corp developing high frequency signal tracking and
active
power
management
solutions
for
semiconductor test devices. During the summer of
2007 he was with Intel Corp. investigating high
performance, small form factor motherboard
architectures to support future PC microprocessor requirements. He is
currently a research member of the Analog and Mixed Signal group at Oregon
State University in Corvallis, Oregon with a focus in the areas of deepsubmicron, low-voltage Analog to Digital Conversion and power efficient
tunable R-Mosfet-C filters.
Mr. Guerber is a life member of the Eta Kappa Nu Electrical Engineering
Society and an Active Wikipedia Electronics Contributor.