Download DESIGN, ANALYSIS AND LAYOUT

DESIGN, ANALYSIS AND LAYOUT IMPLEMENTATION OF
LOW POWER MEMORY BIT CELL IN 90nm TECHNOLOGY
Random access memories which retain their data content as long as electric power is
supplied to the memory device, and do not need any rewrite or refresh operation, are called
static random access memories or SRAMs. CMOS SRAMs feature very fast write and read
operations, can be designed to have extremely low standby power consumption and to
operate in radiation hardened and other severe environments.
SRAM Cell Description:
The basic static RAM cell is consists of two cross-coupled inverters and two access
transistors. The access transistors are connected to the wordline at their respective gate
terminals, and the bitlines at their source/drain terminals.
Nominated power Supply
0.9V
Process Technology
0.09 um CMOS process
Design:
We have designed schematics and layouts of 6T-12T SRAM cell. In order to have a successful
design, transistor sizing is the most important consideration. As a general statement, the
NMOS portion of the cross coupled inverters should be the largest portion of the cell and
the PMOS portion of the cross coupled inverters should be the smallest.
Here we evaluate the stability of a SRAM cell by evaluating Static Noise Margin (SNM) .SNM
is defined as the minimum DC noise voltage needed to flip the cell state, and is used to
quantify the stability of a SRAM cell using a static approach.
Result:
SRAM provides high SNM when we use 12 transistor SRAM cell and obviously power
consumption will be less in case of 6T SRAM cell but maximum power is consumed by 11
transistor SRAM cell.
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