Download ECE 4340/5340 VLSI Design I, Final Exam

ECE 4340/5340 VLSI Design I, Final Exam.
Answer all the questions.
Name _________________
I. a) Determine the propagation delay for the CMOS gate which implements the
function F= A(B+C)+BC . Cload= 1pf. VDD= 5V, VTn= 1V, VTp=-1V.
k’n=40A/V2, k’p=20A/V2
All the MOSFETs have W/L=2.
b) If the output of the above gate is connected to a metal interconnect film of width 1
micron and length 500 micron, and the oxide thickness is 0.3 micron, what is
the resistance and capacitance offered by the interconnect if the sheet resistance of
interconnect is 1 ohm per square.
If you use a simple RC circuit model, what is the delay due to interconnect assuming
Step input voltage at the output of the gate.
c) If the input signal is a step pulse (Vin) connected to the following RC tree, determine
the delay at node 8. Assume each resistor =200 ohms, and C=0.2pf.
II. a) What are advantages and disadvantages of static logic over dynamic logic.?
b) Implement the following function through dynamic logic.
________
F= AB+A B
c) determine the precharge time? Assume parameters given in table 1 and Cload=1pf.
W/L of each MOSFET=1
d) determine the evaluate time.
e) What are the advantages of Domino logic over dynamic logic.
f) Show the circuit diagram of a 4 bit carry look ahead adder. Explain how this adder is
faster than conventional adder.
III.
a) Draw the circuit diagram of CMOS SRAM cell.
b) For the following SRAM cell, determine the output logic voltages. Determine the
static power dissipation for the cell. Assume parameters given in Problem 1.
Suggest methods to minimize power dissipation. Discuss advantages and disadvantages
of this cell over CMOS SRAM cell.
5V
5k
5k
W/L=1
WL
Column
W/L=1
WL
Column
c) Draw the architecture of 64 bit SRAM and explain how the reading and writing is
accomplished.
d) For the following DRAM cell, the bit line is precharged to VDD/2 by using a clocked
pre-charge circuit. Also the ‘Write’ circuit is assumed here to bring the potential of the bit
line to VDD or 0V during the ‘write’ operation with word line at VDD.
VTO=1V, 0.3V 1/2 and |2F| = 0.6V. Use parameter in Problem 1.
Bit line
WL(word line)
W/L=1
Vs
Cs= 50fF
1) Find the maximum voltage across the capacitor Cs after write “1” operation.
Include body effect..VDD=5V.
2) Assuming zero leakage current in the circuit, find the voltage at the bit line
during read ‘1’ operation after the bit line is first pre charged to VDD/2.
3) If the transistor has a leakage current of 1pA, what is the maximum refresh time
so that stored “1” across does not go down below 80% of initial maximum voltage
across Cs.
e) Describe with diagram of flash memory cell for read and write operation.
f) What is the difference between a NAND and NOR flash.
g) Explain briefly with diagram operation of ferroelectric memory.
IV. a) Design a CMOS inverter with average propagation delay of 15 nano secs. The
power supply voltage is 5V. Use the parameters given in problem 1. The load
capacitance is 1 pf. Neglect self capacitance of MOSFETs. Minimum gate length =0.5
microns.
b) Implement the following function using non-standard CMOS logic.
F= AB+BC+CA
What are advantage and disadvantage of non-standard CMOS over standard CMOS.
c) Design a super buffer with a chain of inverters to drive a load capacitance of 10pf and
the input capacitance is 0.1pf.
d) For the following circuit determine the steady state voltages. Threshold voltage
VT= 1V.
1)
5V
5V
Vin=5V
V1=
V2
V1
V2=
2) V1= , V2 =
V3=
4V
3V
V4 =
, V3 =
5V
V3
5V
5V
V2
V1
5V
V4
V3