Download Exercise 6

Exercise 6
Cell and CellView Design
1. Circuit creation
We will use the circuit shown on the scheme below. The coil L0, the resistor
R2 and lead source V0 are ideal elements and they are placed in analogLib
library.
Koplitz generator– DC operation point
The library’s names, the element’s names and the parameters values used in
the circuit are shown in the table below:
Library
analogLib
PRIMLIB
PRIMLIB
PRIMLIB
PRIMLIB
PRIMLIB
PRIMLIB
PRIMLIB
analogLib
analogLib
Element
V0
nmos4
R3
R1
R0
C1
C2
C3
L
RL (R2)
Starting transient analysis
Parameters’ values
Vdc=2.5V
W=100um, number of gates=10
2kΩ
4kΩ
500Ω
3.12pF
3.12pF
10pF
5.83nH
2Ω
Transient additional options
2. Circuit Analysis
In order to check the circuit working capacity we will use dc analysis on the
operating point and transient analysis. To star the analyses go to Analog
Environment in the scheme editor. A simulation window appears. Go to
Analyses  Choose and check both dc  Save DC Operating Point and
tran. For Tran analysis set Stop Time which means end of the simulation
period of time. It has to be enough for the generator to start its work and to
reach constant working regime. Choose such step, maxstep and an
integration method, that the simulator to work properly.
When the simulation is over we can take the results for:
1) DC operating point - Results  Annotate  DC Operating
Points
2) Tran analysis – current and voltage results are visualized in the
transistor’s drain and source - Results  Direct Plot  Transient
Signal
Tran analysis results
3. Circuit preparation for its layout
In order to create a layout you need to prepare the circuit at first. To do that,
copy your circuit in a new cell from the library you are working in. All
elements should belong to the library that is connected with a technology
process. In our exercise we use PRIMLIB which contains real elements for
0.35m CMOS technology for AMS. The ideal elements are the coil, the
resistor which controls the circuit serial resistance, the power supply and the
ground. All these elements do not have a layout and should be removed
before to place the circuit in the layout editor. The ideal elements will be
added externally on a later stage when we do the circuit simulation after
creating a layout (re-simulation).
Kolpitz generator will be design as a standard cell. Therefore after we
remove all ideal elements, we should add pins which will be the circuit’s
outputs. That way the created cell can be used as a constructive element in
higher leveled hierarchical circuits.
Kolpitz generator, prepared for a layout design
In order the re-simulation to be possible it is necessary the circuit to has a
symbolic view. Therefore we are making a circuit symbol (visit exercise №4
for more details). We are creating a new cell containing that symbol plus all
ideal elements in order to verify once again the circuit functionality after the
changes are made.
4. Layout
1)
Schematic to layout view elements shifting
We will use the Kolpitz generator to create a layout. Go to Tools 
Design Synthesis  Layout XL.
Cell name box is automatically filled. Make a check if the used tool is
Virtuoso and press OK. A Virtuoso XL window has opened. In that
window, go to Design  Gen from source.
In the form Layout Generation set the pin sizes and the layer which
should be used in the layout. The form is filled with default parameters
but they can be edited as well. Press the button Ok in order all circuit
elements to be automatically filled in the layout editor window. On
this stage you can see only the elements’ outlines. In order to make all
layers visible press buttons Shift + f.
The window LSW (Layer Selection Window) was opened
simultaneously with Virtuoso XL starting. In LSW all layers, which
can be used in a layout, are shown. There is an option to include
and/or exclude layers from a list. That comes possible with command
Edit  Set Valid Layers.
2) Suiting elements in a circuit
After starting Virtuoso XL and placing all the elements that should be
used, we have to order those elements in their proper places. All
elements should be placed in areas surrounded by a prBndry dg layer
and all the pins should be placed on the edges. To do this, go to Place
 Pin Placement. Regarding the elements placing do not forget the
wires that will be added on a later stage. CADENCE allows
visualizing the logical connections between the elements.
(Connectivity  Show Incomplete Nets).
The shape of the elements can be changed not only in the schematic editor
Virtuoso Schematic Composer (Edit Properties form), but also in the
layout editor Virtuoso Layout XL. All changes that are made in the layout
editor should be transferred to the schematic one as well. This can be
automatically done using the command Connectivity  Update 
Schematic Parameters. The elements that have been changed should be
selected before the command implementation.
The elements placing in the circuit depends on the circuit characteristics,
the designing rules and all the limitations coming from technology using.
3) Elements’ wiring
After all the elements are properly placed we need to connect them with
wires. From LSW choose a layer where to set the wires. In most cases the
first metal layer is used (MET1 dg). Go to Create  Path or press button
p from the keyboard.
By default the wire width is the minimum possible number. It should be
changed according to the amperage which the wires should endure. In order
to avoid any wire crossing use other layer to place the rest of the wires. Use
command Change To Layer from wire creation form.
The most recently used keyboard commands are shown in the table below:
Shift-f
Ctrl-f
Shift-z
Ctrl-z
g
m
command +F3
k
K
W
i
q
F4
u
All layers become visible
Makes visible only the elements outlines
Size decrease 2 times
Size increase 2 times
On/Off grid gravity
Move/rotate objects
Additional options to a command
Draw a line
Erase a line
Further view
Insert element
Call a window with elements’ parameters
Switch full/ particular selecting regimes
Undo
4) Some useful advices for easier layout creation
 Usually the pins for power source ground are placed on opposite
sides of the layout.
 The distance between the elements should be as small as possible
but big enough to follow the design rules.
Kolpitz generator layout
5. Layout verification
For layout verification in CADENCE we use a product called Diva. It
contains few tools for physical verification which allow errors finding and
their rectification.
1)
Design Rule Check (DRC)
After the wiring is done, the layout should be check if all design
rules are followed. From Layout XL window Verify  DRC.
Error finding comes possible with command Verify  Marker 
Find. If some error appearance can not be explained then go to
Verify  Marker  Explain.
2)
Elements extraction from the layout.
The next step is to extract the schematic and parasitic elements
from the layout. For the extraction we use the process of frame
identification as we create a symbol for each identified frame. The
symbol is placed in extracted schematic view which is generated
with each program starting. An identification rules are needed to be
defined, in order any parasitic influences to be located.
This verification program provides with tools for indentified frame
parameters measurements, makes calculations with those
parameters and keeps the result as a parameters value in the
extracted scheme. Furthermore this program makes the same with
the parasites and keeps the calculated value as parasitic parameter
of some element or as parasitic frames between the pins. The
values of these parameters are accessible for other CADENCE
modules as well. As an example is Netlist generating program. This
is necessary in order the re-simulation to be possible. Parasites are
all those frames which are in the layout only as a secondary effect
in a circuit design process. An example is the parasitic capacity
which comes from re-covering of two metal layers. Its value is
calculated with taking the dimensions of the re-covered surface.
In order to start the extraction, go to Verify  Extract. From the
window Extract press the button Set Switches in order to turn on
the switch capall. If this switch is not turned on then the extraction
program will recognize only the circuit elements, without the
parasitic ones. Press the button Apply, or OK.
After the extraction implementation a new cellview (extracted)
appears in the library browser Library Manager. The extracted
view is similar to the schematic one, but with parasitic capacities
included. It is necessary for the next step of the design process – resimulation.
3)
Layout Versus Schematic – LVS
LVS compares two kinds of cellviews and shows the differences
between them. Most frequently LVS compares extracted and
schematic view. The module creates a netlist for each view and
compares them following the specified rules.
The LVS starting is from extracted view window through the
command Verify  LVS.
If both views are opened in the moments of LVS starting, then the
form will be automatically filled. Otherwise you should type the
cell and view name. To start the comparison press the button Run.
The comparison may take few minutes. When it is over a new
window with a message Analysis Job Succeeded will appear. That
means that the process of comparison is successfully validated. If
the process is unsuccessful, press the button Info in LVS form in
order to open the log file. In this file all the implemented
commands are written and you can easily find the error reason.
If the comparison is successful, then press the button Output in
order to open a text file with output data from the process. If there
is a message “The net-lists match”, that means that created layout
matches the circuit, but if the message is “The net-lists failed to
match”, then most probably there is an error in the scheme wiring.
In order to find the errors press the button Error Display in LVS
form. A new Error window appears. Press the button First and in
Display box you will see a message for the first error.
Simultaneously in the extracted view the mistaken objects become
lightened.
6. Re-simulation
For the re-simulation we will use the cell containing the Kolpitz generator
symbol with a coil as an external element. Go to Tools  Analog
Environment. In order to use the extracted view for the simulation, or in
other words to make the re-simulation, go to Setup  Environment. Start
the analyses on the circuit again.