Download CMOS INVERTER

CMOS INVERTER
Using Mentor Graphics
Sarah E. Harper
October 12, 2002
EE584 HW6
Table of Contents
Objective ............................................................................................................................. 3
Design Architect ................................................................................................................. 3
Quicksim II ......................................................................................................................... 4
IC Station ............................................................................................................................ 4
Parameter Extraction ........................................................................................................... 6
Accusim .............................................................................................................................. 7
Conclusion .......................................................................................................................... 7
APPENDIX A ..................................................................................................................... 8
APPENDIX B ................................................................................................................... 13
2
Objective
The purpose of the design project was to lay out and test a simple CMOS inverter using Mentor Graphics
and its associated tools. The circuit symbol for the typical inverter is shown in figure 1 below, and Table I
shows its functionality.
Table I
Inverter Functionality
Input
Output
1
0
0
1
Figure 1
Design Architect was used to first create a schematic, choose a symbol, and create a viewpoint. Quicksim
II was then used to simulate the inverter created in design architect to ensure that the design actually
produced the desired outputs specified in Table I.
The design process then proceeded to the Mentor
Graphics IC Station where the layout of the actual NMOS and PMOS transistors was done. Once
completed, this design was checked for design rules, and verified by comparing the layout to the schematic
in LVS. Lastly, a thorough analog simulation was performed, showing the timing and functionality of the
circuit with all of its parasitic capacitances.
Design Architect
Design Architect was used to create the circuit level schematic for the inverter. The NMOS and PMOS
transistors in the schematic came from the SDL Parts in the ADK Libraries. The PMOS (p-fet-4) was
placed above the NMOS (n-fet-4) as shown in figure 2 below. Ground and VDD, also from the SDL parts
list, were added to the circuit, along with input and output ports, and the entire circuit was then wired
together. Figure 2 shows the final schematic.
Figure 2
3
It is important to note that all four channels of the transistor were connected, including the
substrates, which went to VDD and Ground for the PMOS and NMOS respectively. The gate length and
width of each transistor were set as specified to 10/2 (W/L) for the PMOS, and the default 5/2 for the
NMOS. Here the numbers stand for lambdas, or “L’s, and the feature size, which is the length of the gates,
is 2. The sheet was then checked with defaults to ensure good connections, and the design was saved.
A symbol is necessary in order to hide lower level details from higher level designs. A symbol
shows, as seen in figure 1, only the inputs and outputs, and makes placement in other circuits very simple.
The symbol created for this inverter is similar to the traditional inverter symbol. It is shown below in
figure 3.
Figure 3
In order to proceed further with the design, at this point a Viewpoint was created directly from the
Unix command line.
Quicksim II
The functionality of the schematic was tested by using a digital simulator to apply high and low
voltages to the circuit and observe outputs. The following time value pairs were chosen to be applied to the
input of the circuit:
(0,0), (1,10), (0,20), (1,30), (0,40)
Here, the first number is the voltage to be applied, and the second number is the time at which is to be
applied (in nanoseconds). The input and output signals were then chosen as signals to trace. The
simulation was then run, and the output waveform appeared as shown in figure 4 below.
Figure 4
The output here is shown as a dotted line, and the input as a solid line. It is clear from the figure
that when an input goes high, the output goes low, and when the output goes drops low, the input goes
high. This is the expected output of the inverter described above in Table I. Once the functionality of the
schematic was verified, the design proceeded to layout.
IC Station
The actual layout of the inverter was done in the IC Station. To setup the project, the “ami05”
library was chosen, the “ami05” process was chosen, and the “584.rules” rules file was chosen. Another
important setting that was made involved changing the spacing of the grid on the main design screen to .5
4
lambda between each dot. The default for the program is a 1 lambda spacing. Since the minimum feature
size is 2 lambda, a .5 lambda spacing makes the design easier to see and lay out. This setting must be
saved under the “saved settings” options.
The shapes option was used to add different layers in building the transistors one at a time. The
NMOS was built first by applying the following layers according to design rules: Active, Poly, N-Select
and P-Select. The PMOS was built next with many of the same layers and the addition of an N-Well layer.
Lastly, the contacts and metal connections between the two transistors were added. The completed layout
is shown in figure 5.
Figure 5
The spacing of the NMOS and PMOS was adjusted, as shown in the figure, so that the exact
spacing between the top of the power bar and the bottom of the ground bar was 50 lambda (or 50L). This
spacing is known as the pitch and is important to keep constant among circuits so that the smaller circuits
can be instantiated into larger circuits with little difficulty. As in the schematic, the PMOS is above the
5
NMOS. The source of the PMOS has its contact connected to the metal VDD layer, and the source of the
NMOS has its contact connected to the ground layer. The vertical metal layer in the middle serves to
connect the two transistor drains as is done in the schematic of figure 1.
For this project, a set of lambda rules was used for design rules. These rules, though somewhat
loose, are simple and ensure that at maximum displacement, there is no overlapping between different
circuit layers causing shorts and other electrical and physical problems. The Design Rules Checker was
used to check the circuit for compliance with these rules. It checked for things such as size of connectors
and distance from active to n-well. All errors found by the design rules checker were corrected by
modifying the layout with editing tools such as notch, move, and stretch.
Lastly, the layout was verified using the Layout Vs. Schematic checker (LVS). This is the final
check to ensure that the layout of the different pieces of the transistors actually matches the schematic
originally designed. It checks that there are the same ports and nets. Errors found in the LVS check are
often the most difficult to find and correct. In this project, however, the LVS check passed correctly. The
LVS report can be found in Appendix A.
Parameter Extraction
Different layouts of a circuit in the IC station directly affect the parasitics in the circuit. The
Parameter Extraction step is used to measure and back annotate these parasitics. Basically, it is finding the
parasitics associated with a particular layout and adding them to the schematic created for the circuit. This
allows a user to do a very accurate analog simulation in Accusim. In a process called “Lumped Extraction”
the parasitics were summed together at each node. Settings for this extraction were specific and are
detailed in the Parameter Extraction Tutorial. The result of the parameter extraction was the inv.xfd file
shown in appendix B. It shows all timing delays and the resistance of each path in the circuit. Figure 6
shows the result of the new parasitics being added to the schematic diagram of figure 2.
Figure 6
6
Accusim
Once the schematic held information concerning parasitic capacitances in the circuit, a precise
simulation of the circuit was run using Accusim II. The results of this simulation are shown in figure 7. As
shown, the new waveform is slightly different than the quicksim simulation of figure 4. The parasitics due
to the physical layout result in the rise and fall times visible on the accusim simulation.
Figure 7
The bottom waveform is the input applied by Accusim to the circuit. It is a pulsed waveform with
a period of 100 nanoseconds and a height of 3 volts. The top waveform shows the circuit’s reaction to the
input. As expected, the output shows the inverted input. The rise time of the top waveform was measured
to be .394ns, and the fall time was measured to be .476ns. These values are more than 1ns less than those
predicted in the design tutorial.
Conclusion
The final circuit designed was a functioning CMOS inverter. The design flow started with a
schematic and followed through to transistor layout and finally testing. The design was a good introduction
to the Mentor Graphics tools, leading through the many detailed steps and software packages necessary to
fully design and test a circuit. The simulation tools showed how different layouts can affect the timing of a
circuit. Designs must be modified to create a small rise and fall time, and thus a circuit that works very
closely to its theoretical design. The design process learned can be repeated for other simple, and more
complex circuits. Creating the symbol makes it easy to incorporate the simple inverter into higher level
designs. The inverter cell built can now be used as a building block for more complicated circuits.
7
APPENDIX A
##################################################
##
##
##
C A L I B R E
S Y S T E M
##
##
##
##
L V S
R E P O R T
##
##
##
##################################################
REPORT FILE NAME:
LAYOUT NAME:
SOURCE NAME:
RULE FILE:
LVS MODE:
RULE FILE NAME:
CREATION TIME:
CURRENT DIRECTORY:
USER NAME:
/class/ee584/seharper/invdir/lvs.rep
/class/ee584/seharper/invdir/inv
/class/ee584/seharper/invdir/inv/sdl
/class/lib/584.rules
Mask
/class/lib/584.rules
Sun Oct 13 15:39:06 2002
/export/home/class/ee584/seharper/invdir
seharper
***********************************************************************
***************************************
OVERALL COMPARISON RESULTS
***********************************************************************
***************************************
#
###################
#
#
#
CORRECT
#
#
#
###################
#
#
#
# #
#
_
*
_
*
|
\___/
------------------------------------------------------------------------------------------------------------INITIAL NUMBERS OF OBJECTS
--------------------------
Ports:
Nets:
Instances:
Total Inst:
Layout
-----4
Source
-----4
6
4
1
1
-----2
1
1
-----2
Component Type
-------------*
mn (4 pins)
mp (4 pins)
8
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Ports:
Nets:
Instances:
Total Inst:
Layout
-----4
Source
-----4
4
4
1
1
-----2
1
1
-----2
Component Type
--------------
mn (4 pins)
mp (4 pins)
* = Number of objects in layout different from number in source.
***********************************************************************
***************************************
LVS PARAMETERS
***********************************************************************
***************************************
o LVS Setup:
Component Type Properties:
Subtype Property:
Pin Name Properties:
Power Net Names:
Ground Net Names:
Non User Name Port:
Non User Name Net:
Non User Name Instance:
Ignore Ports:
Check Port Names:
All Capacitor Pins Swappable:
Discard Pins By Device:
Reduce Series Mos Transistors:
Reduce Parallel Mos Transistors:
Reduce Semi-Series Mos Transistors:
Recognize Gates:
Reduce Split Gates:
Reduce Parallel Bipolar Transistors:
Reduce Series Capacitors:
Reduce Parallel Capacitors:
Reduce Series Resistors:
Reduce Parallel Resistors:
Reduce Parallel Diodes:
Unused Device Layout Filter Options:
Unused Device Source Filter Options:
Soft Substrate Pins:
LVS Report Options:
Expand Unbalanced Cells:
9
phy_comp element comp
model
phy_pin
"VDD"
"VSS"
NO
NO
NO
NO
NO
YES
NO
ALL
YES
YES
YES
YES
YES
YES
YES
NO
YES
Globals Are Ports:
Reverse WL:
Preserve Parametrized Cells:
Spice Prefer Pins:
Spice Slash Is Space:
Spice Allow Floating Pins:
Spice Conditional LDD:
Spice Override Globals:
Spice Redefine Param:
Spice Replicate Devices:
Strict Subtypes:
Property Resolution Maximum:
Signature Maximum:
Layout Case:
Source Case:
Compare Case:
Report List Limit:
YES
NO
NO
NO
YES
YES
NO
NO
NO
NO
NO
32
None
NO
NO
NO
50
o Numeric Trace Properties:
Component
Mask
Type
Property Name
Component
Tole- Trace
Subtype
rance
mn
0%
Direct
Property Name
Property Name
instpar(w)
width
w
instpar(w)
width
w
instpar(w)
width
w
instpar(w)
width
w
instpar(l)
length
l
instpar(l)
length
l
instpar(l)
length
l
instpar(l)
length
l
instpar(r)
resistance
r
instpar(c)
capacitance
c
instpar(a)
area
a
instpar(p)
perimeter
p
NO
mp
0%
NO
me
0%
NO
md
0%
NO
mn
0%
NO
mp
0%
NO
me
0%
NO
md
0%
NO
r
0%
NO
c
0%
NO
d
0%
NO
d
0%
Source
NO
o Filter Properties:
Component
Constraint
Component
Filter
Property
Short Source Layout
10
String
Direct
Filter
Mask
Type
Nets
Subtype
All
Name
sch_filter_direct_open YES
YES
NO
YES
NO
sch_filter_direct_short YES
YES
YES
NO
YES
NO
sch_filter_mask_open
YES
NO
YES
NO
NO
YES
sch_filter_mask_short YES
YES
YES
NO
NO
YES
lay_filter_direct_open YES
NO
NO
YES
YES
NO
lay_filter_direct_short YES
YES
NO
YES
YES
NO
NO
***********************************************************************
***************************************
INFORMATION AND WARNINGS
***********************************************************************
***************************************
Matched
Matched
Unmatched
Unmatched
Layout
-------
Source
-------
Layout
---------
Source
---------
4
4
0
0
4
4
0
0
1
1
0
0
1
1
0
0
------2
------2
--------0
--------0
Component
---Ports:
Nets:
Instances:
mn(nmos4)
Type
-----
mp(pmos4)
Total Inst:
o Statistics:
2 isolated layout nets were deleted.
o Isolated Layout Nets:
(Layout nets which are not connected to any instances or ports).
5(8.500,28.500) 6(8.500,7.000)
o Layout Names That Are Missing In The Source:
Ports:
GROUND
11
o Initial Correspondence Points:
Ports:
VDD out in
***********************************************************************
***************************************
SUMMARY
***********************************************************************
***************************************
Total CPU Time:
Total Elapsed Time:
0 sec
0 sec
12
APPENDIX B
##################################################
##
##
##
xCalibre
##
##
##
##
Export Distributed Parameters
##
##
##
##################################################
LAYOUT NAME:
RULE FILE NAME:
CREATION TIME:
/class/ee584/seharper/invdir/inv
/class/lib/584.rules
Wed Oct 9 17:18:34 2002
TIME DELAY METHOD:
Rubinstein-Penfield, signal threshold = 0.7
UNITS:
Resistance = ohm
Capacitance = ff
Time
= ns
Net Handle: 3
Rpath
Tdelay
Source
Sink
--------------+--------------+-----------------------------+---------------------------189
4.05e-05
in
mp0/g
(5.500, 21.500)
(8.500, 36.000)
131
2.8e-05
in
mn1/g
(5.500, 21.500)
(8.500, 11.500)
Net Handle: 4
Rpath
Tdelay
Source
Sink
--------------+--------------+-----------------------------+---------------------------44.4
0.000473
mp0/d
out
(10.500, 36.000)
(13.500, 25.000)
107
0.000557
mp0/d
mn1/d
(10.500, 36.000)
(10.500, 11.500)
62.7
0.000782
mn1/d
out
(10.500, 11.500)
(13.500, 25.000)
107
0.000899
mn1/d
mp0/d
(10.500, 11.500)
(10.500, 36.000)
Net Handle: 2
Rpath
Tdelay
Source
Sink
--------------+--------------+-----------------------------+---------------------------36.6
0.000141
VDD
mp0/s
(7.375, 42.875)
(8.500, 36.000)
62.4
7.08e-05
VDD
mp0/b
(7.375, 42.875)
(8.500, 36.000)
99
0.000462
mp0/s
mp0/b
(8.500, 36.000)
(8.500, 36.000)
Net Handle: 1
Rpath
Tdelay
Source
Sink
--------------+--------------+-----------------------------+---------------------------62.5
9.74e-05
GROUND
mn1/s
(7.500, 5.875)
(8.500, 11.500)
78.1
0.000141
GROUND
mn1/b
(7.500, 5.875)
(8.500, 11.500)
141
0.000692
mn1/s
mn1/b
(8.500, 11.500)
(8.500, 11.500)
13