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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002
81
A CMOS Bandgap Reference Without Resistors
Arne E. Buck, Member, IEEE, Charles L. McDonald, Member, IEEE, Stephen H. Lewis, Fellow, IEEE, and
T. R. Viswanathan, Fellow, IEEE
Abstract—This paper describes a bandgap reference fabricated
in a 0.5- m digital CMOS technology without resistors. The circuit uses ratioed transistors biased in strong inversion together
with the inverse-function technique to produce a temperature-insensitive gain applied to the proportional to absolute temperature
(PTAT) term in the reference. After trimming, the peak-to-peak
output voltage change is 9.4 mV from 0 C to 70 C. It occupies
0.4 mm2 and dissipates 1.4 mW from a 3.7-V supply.
Index Terms—Analog circuits, analog integrated circuits, CMOS
analog integrated circuits, reference circuits, temperature.
I. INTRODUCTION
B
ANDGAP references add the forward bias voltage across
a p–n diode with a voltage that is proportional to absolute
temperature (PTAT) to produce an output that is insensitive to
changes in temperature [1], [2]. The relative weighting of the
voltages added is usually adjusted by trimming the ratio of two
resistors. In standard digital CMOS technologies, models for the
resistors may not be available or reliable. Also, in digital technologies, the area of such resistors is increased because silicide
is often used to reduce the sheet resistance of the polysilicon
and diffusion layers. As a result, the length and area of the required resistors is increased, increasing not only the cost, but
also the susceptibility of the reference operation to substrate
noise coupling. One way to overcome this problem is to use an
extra mask to selectively block the silicide, but this mask also
increases the cost. In some but not all technologies, the silicide
block mask is required in electrostatic-discharge (ESD) protection circuits. This paper presents a circuit solution to the above
problems: a bandgap reference without resistors [3]. This solution eliminates the need for resistor models and may eliminate
the need for a silicide block mask when this mask is not required
in ESD circuits. Also, the bandgap reference described here uses
only MOS transistors biased in saturation or cutoff. The devices
biased in saturation operate in strong inversion, for which accurate device models are usually available, simplifying the design
process, especially in digital CMOS technologies.
Manuscript received November 17, 2000; revised June 14, 2001. This
work was supported by UC MICRO Grant 00-056 with industrial support
from Analog Devices, Conexant, Exar, Intel, Lucent Technologies, Marvell
Semiconductor, National Semiconductor, NurLogic Design, Texas Instruments,
and TRW.
A. E. Buck was with the University of California, Davis, CA 95616 USA. He
is now with MIT Lincoln Laboratory, Lexington, MA 02420 USA.
C. L. McDonald was with the University of California, Davis, CA 95616
USA. He is now with Analog Devices, Inc., Wilmington, MA 01887 USA.
S. H. Lewis is with the Solid-State Circuits Research Laboratory, Department
of Electrical and Computer Engineering, University of California, Davis, CA
95616 USA (e-mail: [email protected]).
T. R. Viswanathan was with Texas Instruments, Dallas, TX 75266 USA. He
is now with Artiman Ventures, Palo Alto, CA 94303 USA.
Publisher Item Identifier S 0018-9200(02)00127-0.
Fig. 1. Schematic of the core of the bandgap reference.
This paper is organized as follows. Section II describes the
concept, and Section III describes the circuits. The test results
are presented in Section IV, and the conclusion is given in Section V.
II. CONCEPT
To produce a temperature-insensitive output, the bandgap refof about 3–6
erence applies a temperature-independent gain
to the difference between the forward bias voltages across two
. Since resistors are not used, the required gain is
diodes
obtained by using ratioed transistors together with the inverse
function technique [4]. The main idea in the inverse function
to
so
technique is to apply a pair of functions and
. In circuit terms, might be a
that
to some
transconductance (possibly nonlinear) that maps
, which is a scaled version of
, would
current . Then
be a transresistance that cancels the nonlinearity in and provides the required gain . Another approach used in this work
so that
. In this
is to choose
is multiplied by in the curequation, the current
.
rent domain by a current mirror using transistors scaled
The scaled current is converted to the output voltage by a prop, which requires less gain but a
erly selected transresistance
. The inverse-function approach
wider dynamic range than
works with any smooth nonlinearity, and knowledge of the exact
functions is not required as long as it is possible to deduce the
proper scaling.
III. CIRCUITS
Fig. 1 shows the core of the bandgap reference. The PTAT
is applied across the differential
voltage
– , which acts as a transconductance . The resulting
pair
using current mirror
–
and
current is multiplied by
– , which operates as a
is delivered to differential pair
0018–9200/02$17.00 © 2002 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002
TABLE I
DEVICE SIZES
Fig. 2.
Schematic of the connections for transistor
M.
Fig. 3. Complete schematic.
transresistance
because of the negative feedback around
.
falls to its minimum of about 0.6 V at the
The voltage
V is maintained at the
maximum temperature. If
, the differential input to
–
is up to about 0.6 V.
gate of
to operate both
and
To minimize the required
in saturation, an intentional mismatch is introduced wherein the
and
are larger than those of
and
aspect ratios of
, respectively, by a factor . To provide a qualitative understanding of the circuit behavior, the circuit can be analyzed
using a simple square-law MOS model. With the transistor aspect ratios given in Fig. 1, the output voltage equation is derived
–
and
– :
from two gate–source loops around
(1)
In traditional bandgap references, a resistance value would be
in this equation. Here, the parameter
trimmed to adjust
is the ratio of the size of the
–
and
–
differential
to
as well as
pairs, and is the current-mirror gain from
the ratio of the tail currents of the two differential pairs. On the
prototype, is held constant while is trimmed by adjusting
and
under digital control. These
the aspect ratios of
transistors are each laid out as an array of devices with binaryweighted widths and equal lengths. These arrays can be adjusted
digitally by means of transmission gates that connect the gates
.
of individual array elements to the appropriate diode or to
is composed of five devices, labeled
Fig. 2 shows that
to
. Transistor
uses a similar structure but with seven
to
in its array.
devices
Fig. 3 shows the complete circuit. To improve the supply insensitivity, it uses a self-bias configuration that is a modification of a previously published circuit [5]. The current that flows
is that which forces
.
is provided by
, allowing the curMost of the current in
to be small enough that
. Therefore,
rent in
, and an equation for the drain current in
is
(2)
–
form a start-up circuit. It consists of
Transistors
–
. If the core
a string of diode-connected transistors
of the reference is off when the power supply is applied to the
turns on and pulls up on the gate of
, turning
circuit,
on the core. When the core turns on, the voltage from the gate of
to ground rises high enough to turn off
, disconnecting
the start-up circuit from the core.
in Fig. 3 repTable I shows the device sizes. Transistor
to
resents the components of the array of transistors
in Fig. 2 that are connected to diode
. The width of trancan vary from 5 to 155 m, and the nominal width
sistor
represents the components of a similar
is 80 m. Similarly,
to
that are connected to diode
.
array of transistors
can vary from 5 to 635 m, and the
The width of transistor
nominal width is 320 m.
and
are actually each formed with a
Diodes
PMOS transistor. For each of these transistors, the gate,
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 1, JANUARY 2002
83
Fig. 6. Measured output voltage versus temperature of four prototypes
trimmed to the same target at 45 C.
Fig. 4. Die photograph.
Fig. 7.
Measured output supply rejection versus frequency at 25 C.
TABLE II
PERFORMANCE SUMMARY
Fig. 5. Measured output voltage versus temperature of one prototype.
drain, and source are connected together. The combined
is connected to the gate of
;
drain–gate–source node of
is connected to
the combined drain–gate–source node of
. The body of each of these PMOS transistors
the gate of
is connected to ground. This approach was selected because
MOSIS provided models for these junctions but not for substrate p-n-p transistors. However, these models may not be
accurate in part because BSIM3 models the source–drain diode
behavior adequately only when the diodes are reverse biased
[6]. To compensate for the possibility that the diode models
are inaccurate with only one fabrication cycle, the trim range
of the prototype was intentionally designed to be much larger
than simulations showed to be necessary. In practice, trimming
may not be required for low precision applications ( 5%) once
the diodes are thoroughly characterized and the nominal gain is
adjusted accordingly.
IV. EXPERIMENTAL RESULTS
The circuit was fabricated in a MOSIS 0.5- m n-well CMOS
process. Fig. 4 shows a die photograph. The area is 0.4 mm
without pads. Twenty-five parts were fabricated and tested at
25 C before trimming. The average output voltage is 1.1219 V,
and the standard deviation is 8.8 mV. Fig. 5 shows a plot of
the output voltage versus temperature for the trimmed reference with the lowest output variation from 0 C to 70 C. The
peak-to-peak variation is 9.4 mV. Fig. 6 shows a similar plot
in which four references are each trimmed to set the output at
45 C equal to the same target voltage (1.1195 V 0.5 mV).
The difference between the maximum voltage exhibited by any
of these references and the minimum exhibited by any of these
references between 0 C and 70 C is 11.4 mV peak to peak.
Fig. 7 shows a plot of supply rejection versus frequency. The
supply rejection is 45.1 dB at 10 Hz. The power dissipation is
1.4 mW from a 3.7-V supply. Table II summarizes the performance.
V. CONCLUSION
This paper shows a bandgap reference circuit without resistors that is compatible with a pure digital CMOS technology.
ACKNOWLEDGMENT
The authors would like to thank A. P. Brokaw and
G. Pietrobon at Analog Devices for their help with the noise
measurement.
REFERENCES
[1] R. J. Widlar, “New developments in IC voltage regulators,” IEEE J.
Solid-State Circuits, vol. SC-6, pp. 2–7, Feb. 1971.
[2] A. P. Brokaw, “A simple three-terminal IC bandgap reference,” IEEE J.
Solid-State Circuits, vol. SC-9, pp. 388–393, Dec. 1974.
[3] A. Buck, C. McDonald, S. Lewis, and T. R. Viswanathan, “A CMOS
bandgap reference without resistors,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2000, pp. 442–443.
[4] R. R. Torrance, T. R. Viswanathan, and J. V. Hanson, “CMOS voltage
to current transducers,” IEEE Trans. Circuits Syst., vol. CAS-32, pp.
1097–1104, Nov. 1985.
[5] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 3rd ed. New York: Wiley, 1993, p. 345, 352.
[6] W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3
and BSIM4. New York: Wiley, 2001, p. 102.