Download Current-Mode Logic

EE241 Spring 2006 Revised Project Proposal
Current Mode Logic
Phillip Chin, Junjie Su, Xiaolan Zhong
Background: With the scaling down of CMOS transistors, many issues, once considered
negligible, now have become a factor in design. The problems we will focus on are to
either reduce or utilize leakage current and to lower power consumption. Our proposed
area of research is to this is instead of doing logic with voltages, using current mode
logic. Current mode based circuits offer many advantage such as reduced number of
transistors and a smaller area [1]. However, there are some drawbacks that we have to
account for such as low fanout [2]. Through research, we hope to find the optimal point
where we can get the greatest performance with the least amount degradation due to
drawbacks.
An area we would like to explore is subthreshold operation. By operating in this region,
we hope to significantly reduce voltage and use leakage current to perform logic. By
working with low voltages and actually taking advantage of leakage current, we hope that
we can obtain the same performance of voltage logic and have low power consumption.
Effectively, we would actually like to take advantage of this flaw in today’s MOSFETs.
Plan: To begin we will research technologies that other people have developed and adapt
and optimize it to today’s technology (most articles we found were from 10 or more years
ago). We will use SPICE to run simulations and Cadence to create a layout. Eventually,
with our results, we hope to apply it to a real device such as an adder or a memory cell.
References:
[1] Ismail Enis Ungan and Murat Askar, “A Wired-AND Current-Mode Circuit
Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC,” Analog
Integrated Circuits and Signal Processing, pp.59-70, November 18, 1996.
[2] K. Wayne Current, “Current-Mode CMOS Multiple-Valued Logic Circuits,” IEEE
Journal of Solid-State Circuits, Vol. 29, No. 2, February 1994, pp.95-106