Download FP7 FET-OPEN i-RISC Innovative Reliable Chip Design from Low

FP7 FET-OPEN
i-RISC
Innovative Reliable Chip Design from
Low Power Unreliable Components
Dr. Alexandru Amaricai
UPT Coordinator
Outline
∗ Project overview
∗ Objectives & scientific goals
∗ Trans-disciplinary approach
∗ Error correction codes
∗ Sub-powered circuit design
∗ Workplan
∗ Workpackages
∗ Error models for sub-powered CMOS circuits
∗ Conclusions
Project overview
∗ Partners:
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CEA-LETI Grenoble – Dr. Valentin Savin (Coordinator)
ENSEA Cergy-Pontoise – Prof. David Declercq
UCC Cork - Dr. Emanuel Popovici
TU Delft – Prof. Sorin Cotofana
ELFAK Nis – Dr. Goran Djordjevic and Prof. Bane Vasic
UPT – Dr. Alexandru Amaricai
∗ Budget
∗ Total budget: 2 161 k Euro / 1 613 k Euro – EU Contribution
∗ UPT budget: 177 k Euro / 133 k Euro – EU Contribution
∗ Duration
∗ Feb 2013 – Jan 2016
Trans-disciplinary Approach
Error Correction Coding
∗ Soft-decoding ECC based
∗ Very good error correction
capability
∗ Close to theoretical Shannon limit
∗ Decoding process
∗ High cost/power consumption
∗ Operates on reliable hardware
Trans-disciplinary Approach
Sub-powered CMOS circuits
∗ Power reduction via aggressive
voltage scaling
∗ Both static and dynamic
components
∗ High latency – undefined timing
characteristics
∗ Augmented effects of PVT variations
∗ Probabilistic behavior of logic
components
Objectives
Error Correction
∗ Is it possible to perform
effective error correction on
low-power unreliable
hardware?
Sub-powered Circuits
∗ Is it possible to perform
reliable computation using ECC
techniques ?
Work-Plan
∗ WP2 – Error Models and
Energy Measures
∗ WP5 – Reliable Boolean
Function Synthesis
∗ WP3 - Fault Tolerant
Algorithms for Error
Correction
∗ WP4 - Reliable Data
Storage and Transport
∗ WP6 – Proof-of-Concept
Error Models for Sub-Powered CMOS
Circuits
∗ Methodology
Dynamic Timing Analysis
Technology models : TSMC 45 nm
Monte-Carlo simulations (10.000 simulations)
Simulations for 0.25V, 0.3V and 0.35 V
∗ Sub-threshold and near-threshold regimes
∗ Setup
∗ Process variations (threshold voltage & oxide thickness)
∗ Supply voltage variations (+/- 30 mV)
∗ Different temperatures
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Error Models for Sub-powered CMOS
Circuits – NAND Gate
Error Models for Sub-powered CMOS
Circuits
∗ Delay dependent probability of correctness
∗ Higher gate delay leads to better reliability
∗ Data dependent probabilities (input switch
combinations)
∗ Unbalanced charging and discharging currents for
different input switch combinations
∗ Probability dependence on supply voltage
∗ Lower supply voltage leads to lower reliability
Conclusions
∗ i-RISC – Trans-disciplinary project
∗ Coding theory
∗ Sub-powered circuit design
∗ High risk scientific objectives for both communities
∗ Effective ECC on unreliable low-power hardware
∗ Reliable logic circuits using ECC coding and decoding