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IEEE JOURNAL 224 Associate Professor at actual field of research aided design. the University of California, is design of integrated-circuits Berkeley. His and computer- OF SOLID-STATE CIRCUITS, Mr. Vanparys has been (IWONL) since 1972. a Fellow Roger Rene A. Vanparys was born in Knokke, Belgium, on May 7, 1949. He received the Engineer’s degree in electrical and mechanical engineering from the Catholic University of Leuven, Leuven, Belgium, in 1972. In 1972 he was employed at the Catholic University of Leuven as a Research Member of the Laboratorium Fysica en Elektronica van de Halfgeleiders. In 1975 he joined the Regie van Telegrafie en Telefonie (The Belgian Post Office). CMOS Analog Abstract –A publications. for simple operating ation design. test Various It circuit describing inversion includes of taking and analyzed: circuits, fier. All these circuits and compatible low-power and is suitable both p- and ntechnology. of weak inversion current detector the result a CMOS references scheme which KNOWN to threshold technology bandpass in order at a low a model valid channel lengths; convari- to digital inversion pointed the ID Bel@rm, voltage appropriate S .A., of that diffusion. channel Van diffusion the behavior operation, The used Barker for small to short current, Overstraeten current in et al. is a function of [4] , and have of MOS with transistors excellent in their experimental has proposed signal of this advantageously technology. mentioned in Section in Section circuit and inversion has derived III. work II and of MOS and reports an circuits. Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. basis, results by Section advantage obtained weak for circuits, model, circuit based design, experimental IV describes of the with in- can be analog simple and suitable taking that transistors interesting A very supported On this configurations behavior is to demonstrate operation to implement in CMOS on previously is derived to use weak amplification paper (or subthreshold) especially version [9] model. purpose version ous Horloger inverters have derived bias and extendable shown this [3] at the source and drain charge Recently, dence 15, 1976. Centre Electronique that of CMOS agreement. nel current threshold region of the characteristics, inside which the device operates with a weakly inverted channel, has been studied by many authors. Barron [1] has developed the pertinent theory and has obtained a solution in closed form by introducing some approximations. Swanson and Meindl [2] have elaborated a similar substrate have by accurately operation This sub - any they flows range of a MOS transistor is reduced below the threshold voltage defined by the usual strong inversion characteristics, the chanexponentially. for the behavior and Chakravarti Troutman has analyzed in more detail the effect of substrate bias [6] and the slope of the exponential characteristics [7] . Masuhara et al. [8] have presented a model in closed form describing Manuscript received November The authors are with the Neuch&el, Switzerland. was born in Zonhoven, out the influence of surface potential fluctuations on vG characteristics [4] , [5] . In subsequent papers, - whole that when the gate-to-source Troutman inversion, the to describe voltage. have demonstrated ampli- and mobility dedicated expression oper- INTRODUCTION decreases approximately Foundation FELLRATH based is then of a very low-power JEAN weak circuits. T IS WELL Cuppens Science on March 10, 1948. He received the Engineer’s degree in electrical and mechanical engineering from the Catholic University of Leuven, Leuven, Belgium, in 1972. He is currently a Research Member of the Laboratory for Electronics, Systems, Automatization and Technology (formerly the laboratory of Physics and Electronics of Semiconductors) at the Catholic University of Leuven, where he is working towards the Ph.D. degree. are in semiconductor teckology. His main interests IEEE, AND of MOS transis- CMOS and a low-frequency are insensitive I. I for advantage two different MEMBER, basis of previous parameters low-voltage an amplitude with two on the experimentally applied to a quartz oscillator with sumption (<O. 1 PW at 32 kHz), ations, only a Si-gate configurations bipolar the dc behavior is derived is verified transistors are described on known model weak This model circuit channel in of the Belgjan Integrated Circuits Based on Weak Inversion Operation ERIC VITTOZ, tors VOL. SC-12, NO. 3, JUNE 1977 evivari- weak experimental in- VITTOZ AND II. FELLRATH: SIMPLE CMOS MODEL ANALOG IN INTEGRATED WEAK 225 CIRCUITS A INVERSION Let us make the following assumptions. 1) The channel is sufficiently long so that the gradual channel approximation can be used and channel-length effects are negligible. k <- -2 Cox .1 0 0,8- 1+ modulation I 2) Generation currents in the drain, channel, and source depletion regions are negligible; sou~ce and drain currents are then equal. 3) The density of fast surface states and the fluctuations of surface potential 1. — 5 I 10 06 15 20 0.4@ are negligible. .13u~ Cox. 340pF/mm2 parameter UJS/UT 0,2 The basic derivation cfi be easily substrate of Barron extended voltage. to () 1 ~qe~nj may may then be used and case of nonzero His approximate weak inversion current channel transistor, as ID = SpU; the [1] expression then for e - , 0 I -50 conductor shape factor of the transistor (effective of carriers in the channel, y of Si, ni = intrinsic VS = source-to-substrate voltage, V~ = drain-to-substrate voltage, VG = gate-to-substrate voltage, and ID = drain current. Corresponding values of the surface potential l’ have been reported along the curves. It can be seen that CG is fairly constant for 4UT+@+VS< that is within [3, eq. (1 6)] or from the (6) a range A#~ = @- 6UT of $S included in the to (5), ~S is linearly depending on VG inside this range and (4) takes the simple form 4UT+$+VS<$$<2q)+VS (2) ID =SIDOe for which $~<2@+VS-2UT limits of validity (2) of (4), which corresponds to more than three orders of magnitude for ID if@ >13 UT. According It is valid for that is within The first part of the curves to a decrease of CG with increasing VG is valid channel as long as V~ > VS. for the whole along the channel in weak This result can also be derived from results summarized in [8, table I] . (5) Cox of fast surface states. corresponding carrier concentration, constant .l_g co. Cox + c’ density @= UT In (NB/rzi) bulk Fermi potential, NB = constant bulk impurity concentration, I)S = surface potential, inversion [1] , 2(J’ where CG is the gate capacitance per unit area. Fig. 1 shows typical normalized CG - VG curves calculated [10] at the source end of the channel by assuming a negligible UT= kT/q, es = permittivit 150 total surface capacitance per unit area C’. Therefore, —. i)v~ width over effective length of the channel), p = mobility 1 100 50 (1) where S = geometrical !E!m of the curve. The slope factor n is closely related to the value of this minimum. uT)’/2 _ ~-(v-D/uT)) . (e-(~wd “K Fig. 1. Normalized CG - VG curve at the source end of the channel calculated for typical parameters. The range A$$ of surface potentiat corresponding to weak inversion operation is located at the minimum -(3@/2?YT) (~, 300 an n- ~*JuT 1/2 . source-to- (25) for the be rewritten, T a range ~ - 4UT of OS below the value 20+ strong inversion VS starts at the source end of the channel. On the other hand, the surface depletion be expressed as [4] capacitance Cd can VGinUT(e-(VS/uT) where IDO is a characteristic As a negligible - e-( VD/UT)) (7] current and n a Slope faCtCrr. density of fast surface states is assumed, C’ is equal to cd within the range of interest and (5) yields the slope factor n=l+g (3) As shown in Fig. 1, n can be evaluated at the minimum It maybe inserted into (1), which yields ID =SpU~Cde ‘(20/uT) etisluT (e-( vs/uT) CG - VG curve for which tially depending exponentially on of cd with IJJJUT. $. z 24 + Vs - 4UT, of the so that (3) and (8) yield - e-(vD/uT)). (4) Due to the very S1OWvariation (8) c“0x ~~, ID is essen- Variations of the gate-to-substrate voltage VG are shared between the oxide capacitance per unit area COX and the semi- n. 1 1- (cG/C..) .l+~’ min 4fvB es C..A ( 2(20 - 5UT + VS) ) 1/2 (9) “ This result may be deduced directly from [7, eq. (10)]. Thanks to the slow variation of cd with v., the slope factor n may be considered as a constant for transistors biased by Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. 226 IEEE similar values of VS. IDO for current The same is true transistors IDO is very poorly on controlled the for same Meanwhile, f] np 10-7- ducible parameter available for circuit design. As shown by (9), n takes different values for transistors 10-8- biased by widely 10-$ different values of V~. The same is true for applied to transistors ceeding a few of drain current with UT. differential This is not ratios can only be ,.10 values of V~ not ex- a real limitation + to design flexibility, as will be demonstrated by examples in Section IV. Expression (7) is seen to be symmetrical in VD and V~, as can be expected from the symmetrical structure of the device. It is applicable to p-channel transistors as well by changing the signs of VG, V~, and VD. The transconductance in weak inversion is 1.0 0.5 ‘m . ID = 3VG 1.5 Fig. 2. Gate transfer characteristics measured for I VD I - I Vs I >> UT; the slope factor n is slightly decreasing with increasing reverse sourceto-substrate voltage I Vs 1. TABLE I ME C,SLIRED AND CALCULATED 81D 1977 JUNE // designs must be based on drain current ratios, as is common practice for bipolar circuits. On the contrary, n is a repro- so that the technique CIRCUITS, I DIIA] ,.-6 from batch to batch and, there- fore, its absolute value is of no use to the circuit designer; the l~o, OF SOLID-STATE ,0-5. the characteristic chip. JOURNAL VALUES OF n UT (lo) nUT” For VD - V~ >> fined as n-channel UT, a source transconductance can be de- nUT [mV] Vs=o vs = 0.65 V Vs=o vs = 0.65 V 48 47 39 41 34 40 40 35 Measured Calculated MD _ ID p-channel (11) gms-=s-~” The upper limit of validity in (4) the upper by its value limit taken for (7) is obtained of I)s given from (8); this by (6) and by replacing yields, for III. by introducing Cd VD - VS >3 UT (saturated drain current), n-1 [D < -J- (12) Spcox u;. The have been value of S ensuring weak inversion can be calculated operation the factor (n - 1)/ez can from this relation; be dropped if a rough order of magnitude is all that is needed, so that this upper limit is a direct function of the strong inversion transfer parameter (13) B = Spc’ox. Van Overstraeten fluctuations istics may [5] , but [11 ] . The et al. have affect the of (7) that similar are: 2 “ 1015 cm-3 still valid, with an in- affected, Anyhow, this controlled analog so that value of n. The of of lV~~ would operating influence qfv~~<< simple dependence value circuits the of cd + COX. model the in weak surface This iV~~<<2 “ 1011 cm-z eV”~ exceed 120 nm. (7) should characteristics make questionable be modified. on the the badly design of states is negligible is always if the oxide as long fulfilled thickness as for does not substrate law sponding ment that the (10) The up to the values slope (7), [12] after . Main doping of processing, a channel measurements limit predicted reported from from are seen to of have been strong (9). the effect the ex- The corre- I are in good agree- It should be pointed out the value of gin/ID inversion, value 1/n UT given by is reached. of the behavior corresponding characteristics follow by (12). in Table it reaches its maximum 3 shows by All in have by (7) siIicon-gate wells ID - VG transfer as soon as weak inversion Fig. transistors curves obtained as ID decreases dicted earlier p-type respectively, width. measured UT. n UT products with and described a CMOS temperature. 2 shows ponential Test and 60-prn VD - Vs >> VS for V~ - VS >>0. is again exponential, to a characteristic with voltage As prea negaequal to UT for both types of transistors. The dc transfer characteristics in common gate configuration are, therefore, identical to that of a bipolar transistor in the common base configuration, which is in agreement with(11 ). characteristics of the Fig. 4 shows the ID - VD output transistors drain inversion. condition Fig. for tive For a nonnegligible density of fast surface states fv~, [2], shape, but the [11 ] , the ID - VG curve keeps its exponential slope factor n is increased. Furthermore, the ID – V’ curve is also length with to the one described n-type TRANSISTORS operation experiment,ally and 5 “ 1015 cm-3, made at room ON MOS inversion COX = 340 pF/mm2. increases until potential on the ID - VD curve no effect is therefore creased and less controllable surface of the ID - VG character- slope have practically model shown verified parameters and DATA of weak technology 20-Lrm The minimum EXPERIMENTAL features voltage cally measured currents equal attained excellent in weak saturate to for behavior UT. inversion. exponentially The maximum I VD - V~ I = drain the a characteristic current is practi- 3 UT, which corresponds to an as a dc current version, the flatness of these output Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. As given by (7), with source. As for strong incharacteristics is degraded VITTOZ AND -6 10 \ FELLRATH: CMOS ANALOG INTEGRATED 227 CIRCUITS % e 26.5 mV ,- IVGI=0.6V IvDl = 2.OV 10”7- 10-8. ] IDl [A] 1 p-channel 109 ,.10 , ]v~l — [rrlv] 10”. 100 200 300 Al/ Fig.3. Source trmsfer characteristics measured forl VDl-l VSl>>Up This behavior in weak inversion isidentical to that of abipolartransistor in common base configuration. I Fig. 5. Circuit diagram of a first current sented in dotted line allow a reduction using a dynamic scheme. “F’7’ [.AI ,0 ‘* -- I -0.2 -0.1 p-ch~nnel, VG. transistors repreconsumption by 1 1 10 reference; of power 0.1 transistors; take advantage of the truly negligible wide range of shape factor S practically further refinements gate current, can and of the realizable. As a first example, Fig. 5 shows a current reference based on a known bipolar circuit [13]. It is made up of a simple badly 0.2 controlled primary reference T2 combined with a current stabilizer (Tl, T3, R). Application of the relation (7) with V. [v] V~ = O (sources connected to a common p-well) and VD >> to transistors TI and T3 yields -0. &3V v~. schemes used for bipolar o UT 26mV --12 I I Fig.4. Output characteristics ofp-and in weak inversion. They correspond transistors as de current sources. n-channel transistors measured to an excellent behavior of the ID3 = % IDI exp s~ where the () RIDI - — n uT subscripts refer (14) to those of the ID3 transistors. reaches a maximum by channel-length modulation effects if the channel length S3 i’?UT .— ~R ID3 ~ax “ ~ is reduced. The differential (15) value of VG for two transistors close to each other has been found to follow a Gaussian law. Standard de- for viations ranging from 10-17 mV for n-channel, and 9-14 mV for p-channel have been measured on a few slices in samples of more than 150 pairs of small size transistors (width 16 m, length 6 pm on masks). This corresponds to a standard deviation of the characteristic current IDO ranging from 23-42 percent. polar This spread transistors circuits. is considerably and is a limitation Meanwhile, mismatch can further Seeking for layout simplicity, to the measurements be considerably sistors and optimum larger reduced that design using of bi- of analog suggest by that larger this tran- techniques. we shall assume IDO in the derivations than perfect matching of of Section IV; as shown by (7), the spread of IDO is equivalent to an equal spread of the shape factors S. Statistical measurements deviation of (CG/CO~)~in over 16 batches of the slope factor n smaller than EXAMPLES OF CIRCUITS INVERSION The well-controlled transistors ID1 at ID1 is obtained by centering value of opt. Fig. 6 is a microphotograph mentally the nominal of this circuit integrated experi- with S1/S3 = 10, The resistance R of nominal value 70 kfl has been implemented as a strip of p-well. To reduce the total power consumption without increasing the value of R, two transistors Tq and T5 (represented by a dotted line on Fig. 5) have been included to pulse the current ID I by the low cycle clock CP; ID3 is kept constant by the gate ca- duty pacitance of T3. This advantage would not be available in are reported in technology. Experimental Fig. 7 for results continuous on one sample operation. Both circuit ID1 and ID3 have been measured as a function of the supply voltage Vcc. Although the primary reference current IDI is very voltage dependent, 5 percent. excellent Stabilization bipolar yield a standard IV. (16) dc current operating exponential source in weak BASED ON WEAK OPERATION transfer behavior inversion characteristics of both suggest types some and of MOS circuit ID3 is constant within 15 percent in the range 2.6 to 3.8 V for which the circuit was designed. Measurements on 40 circuits yield an average value of 27.7 nA for ID3 ~m, which is close to the theoretical value of 25 nA calculated from (1 5), and a standard deviation Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. of 11 nA. 228 lEEE JOURNAL OF SOLID-STATE JUNE 1977 VR R I1 CIRCUITS. 01 1 00 Fig. 8. Circuit Fig. 6. Microphotograph showing the circuit experimentalty. of Fig. diagram of a second current reference. Voltage VR is fully defined by the slope factor n of n-channel transistors and by the various shape factors, 5 integrated ~’o !1 1DS ‘“’’’A’! t [.A] 1D3 30 ..l:d~z!.[mv] : 40 30 % . 10 53 10 R a / b 1. 20. ‘D1 =70kn >. s, 10 %=4 s/. Vcc[vl 3 Vcc[vl —Y 0 < 2 Fig. 7. Measured D.1 ~~ 3 characteristics Fig. 9. Experimental ? 4 of the circuit if mirror the current These nected loop, into two higher gains. than until a closed This an equilibrium one by the voltage If T1 and voltage gain T3 operate can be calculated current small when the 17R across resistance in weak from mirror mirrors in both inversion, the previous two of the product () .*. currents is chosen branches increases is reduced the model, a total current drain of less than 1 flA is possible with a value of resistance R below 100 k~. In practice, this reference resist or can be realized as a strip of p-well. As in the previous circuit, the power consumption can be reduced further by voltage saturates at a value very close to UT or nUT, depending on the way the substrate of T3 is connected. As another This circuit equilibrium assuming rored by example, Fig. 10 shows an amplitude detector. is biased by a reference current lR which is mirTz and T4. The various shape factors are chosen such as S3/S1 > S4/S2, so that the drain current of T3 overcomes that of T4 for zero amplitude UI of input voltage Vin; the dc output voltage is then zero. As amplitude UI increases, the average gate vohage ~G~ of T1 must decrease to keep the average current drain of this transistor constant in spite of the nonlinear transfer characteristics (variations of drain voltages of TI and Tz are avoided by the capacitor C3). The (17) ac component is filtered out by R2 C’2, therefore, VG3 = ~G~, hence, the drain current of T3 decreases as U1 increases. As U1 reaches a critical value U1c, the drain current of T4 overcomes that of T3 and Vout jumps to Vce. For () to O. The reference current proportional to VR/R is extracted by the current mirror T4 - T6. Thanks to the small value of VR, to R. and VG3 = VGI –, VR and the result is VK=nUTln connected of the supply voltage Vcc on a circuit made up of discrete selected transistors. It is seen that this normalized reference If T3 is in a separate well connected to its source, then V~3 = O s~ S2 —“— . SI S4 p-well circuit corresponding to to its source; (b) TI and of that the supply voltage t’cc is high enough to ensure drain current saturation of Tz and Tq. If T1 and T3 are in the same p-type well, then V& = V“ and VG~ = t’G~; the application Of relatiOn (7) tO these tWO transistors yields the equilibrium voltage vR=uTh: results on a discrete a special p-well connected in R gain are intercon- gain T3 using a dynamic scheme. Fig. 9 shows the reference voltage VR normalized to the logarithm of the low-current loop gain, measured as a function n-type the resistance gain being for the current The so that current the loop is reached, drop S2/S4. enough two loop one, so that gain a second is small can be neglected. the of T1 and T3 form transistors S3/S, current (a) in Fig. 6. Another current reference based on a known bipolar circuit is shown in Fig. 8. The two p-type transistors Tz and T4 a first 9; T3 in a common shown The latter corresponds to the statistical mismatch of IDO reported in Section III and can be reduced by an increase in size of the transistors. form Fig. (18) TI a sinusoidal and (sources signal U1 sin wr, and for transistors weak inversion with V~l = V& = O to a common p-well) and VD, >> UT, the input T3 operating connected in Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. VITTOZ AND FELLRATH: CMOS ANALOG INTEGRATED CIRCUITS 229 I Fig. 10, Circuit diagram of an ac amplitude I t Low-current Fig. 12. quartz oscillator using the scheme of Fig. 10 for amplitude limitation. I u,~ * 5 L: detector. 32- S3 52 —.. + s, s~ 1- o. 0 Fig. 11. drain 10 Theoretical 20 threshold UIC sinusoidal of the signat. of T1 may be written current IDI =Sl IDO exp from vGq + UI sin @ ( amplitude n UT detector for a (7): ) . 7 (19) Fig. 13. Microphotograph showing the oscillator of Fig. 12 integrated experimentally; output amplifier is not included; R 1 and R z are implemented as lateral diodes in the polycrystalline gate layers. averaging over one period gives ~D1= SIIDO consumption. e ‘G3’”UTI’’(2)=%J’’(%) where 10 is the O-order modified ’20) Bessel function ing ~D ~/ID3 to S2/Sq yields the following [14] relation . Equat- defining the critical voltage UI c: perimentally version operation, the amplifier UIC of the detector depends only on the well- voltage n UT and the various shape factors. As naturally transition range 1-10 Gfl as soon as it exceeds 4-5 nUT. Fig. 14 shows experimental It is seen that the amplitude This circuit has not yet been integrated in this form, but the scheme has been applied to stabilize the amplitude oscillator, as shown in Fig. 12. of a quartz The quartz resonator QR, the transistor 7’1, and the two capacitors C3 and C4 constitute a Pierce oscillator biased by the resistance R 1 and the current source T2. The dc gain of the closed loop made up of transistors T1, T3, T4, and T2 is higher than one so that the currents in both branches increase to high values limited by the output characteristics of T2 and T3. The drain current ~D~ of T1 is high and, therefore, oscillation builds up. As the amplitude U1 at the gate of T1 reaches the value U1c given by (21), ID1 suddenly falls down to the value just necessary to keep this amplitude of oscillation. This value corresponds by relation (1 O) to a transconductance of T1 somewhat larger than the critical oscillation; version the maximum is, therefore, used value of gin/ID advantageously gm 1 transconductance reached to in weak reduce for in- power diodes ex- high as a This type of diode is A differential at every p to n resistance in the at zero voltage has been measured on 10-Mm width in Fig. The noncritical is implemented lateral diodes. of the gate layer. integrated of T1 and T3 has been with silicon-gate technology 11, UI c becomes fairly insensitive to the shape factors (and to fluctuations of the characteristic current ~D’0) shown to reach the logic stage. To ensure weak in- the channel width quad of polycrystalline obtained controlled without increased by the use of closed structures. value resistance R z of the low-pass filter (21) The threshold The signrd can be amplified swing by the directed coupled stage T5 - T6. Fig, 13 is a microphotograph of this oscillator fabricated with the doped-oxide technology [12] . The biasing resistor R, is a single lateral diode. results obtained with this circuit. of oscillation UI at the gate, and the current drain 1, are both fairly independent of the supply voltage Vcc in the range of 1-3 V. The amplitude is very close to the calculated critical value Ulc. With the t ypical values of components chosen for the experiment, the current drain is of the order of 30 nA. Another 60 nA would be sufficient for so that a total current of less than the output amplifier, 100 nA is feasible. The current increases to a much higher value if the quartz is removed. Due to the quasi-independence of Ulc on the current level, the current value. has a tendency This can be easily resistance reduces to avoided fluctuate of a few 100 kf2 in the source the feedback gain but around by adding its nominal a noncritical of T3. series This resistance has a negligible effect on the amplitude. Weak conditions inversion operation of an amplifier, can help and hence, Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. to control its frequency the biasing response. IEEE JOURNAL 230 / lo- t / / medium / 1 [A] U, [mvl I I ,’ (wihout high frequency / lo- AH= (24) -gm7/ja(Cz + CS). (25) of expressions (7) and (22) yields quartz) u, VG5[n~ ID05 +=s5— 5 / / I I JUNE 1977 000 t / / CIRCUITS, A o = - /R~, frequency The combination I OF SOLID-STATE UT UT ~-(VS5/UT~ (26) e — where ID03 and ns take special values due to the large value of ‘JIC — VS5. If the condition 00 (calculated) I 1 I (27) 1 I 1 1 V& = VS5 so that is fulfilled, T3. lo- 0 ID05 and n~ are also valid As VG3 = VG5, the combination to transistor T3 yields the simple of (26) for and (7) applied result (28) On the other hand, (1 O) gives Vcc[vl lo- o 1.0 (29) 20 Fig. 14. Experimental results obtained with the circuit shown in Fig. 13; amplitude of oscillation U1 and total current I are fairly independent of the supply voltage VCC. A standard watch quartz resonator with quality factor Q is used. Therefore, defined the frequency by the well-controlled tors. response reference lR, parameters In particular, of the amplifier the various is entirely shape factors, n and UT, and the various the medium the capaci- gain per stage A ~, frequency given by (24), becomes (30) IJIR I — V. CONCLUSION T3 The T, C* == I dc behavior version can be described circuit design. and contains closely I reference (a) and one stage (b) of a multistage band- pass amplifier. As an example, made Fig. up of a cascade age reference by a current The basic bandpass amplifier stages (b) and a single volt- to all stages. The circuit is biased lR. parameters defining the frequency capacitors, output the transconductance resistance of one gm 7 of R ~ of T5 is defined as (22) VS5) VD5 . VS5 for only slightly AL = -juCIR~, (23) and therefore, transistors having of experimental CMOS implemented show for value current batch, but n which IDO reasonably Both Vs. is conare voltage be taken only The behavior for of MOS aspects comparable with advantage the the n and IDO source-to-substrate must of is which is in many based that in designing a very are found described on this of analog to a truly CMOS low-current other quartz both dc and a applications. and mobility a low-voltage circuits. technologies as such as an oscillator, to threshold with to digital CMOS Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply. circuits: to be very attractive compatible as well to take advantage and ac circuits, are insensitive dedicated model, it is possible references, and are fully with suitable current. results, technology in- experimentally minimum different inversion detector, The circuits the in weak the slope factor values considerations amplifier to on widely such as current variations, batch model verified characteristic transistors behavior bandpass only: different control Theoretical simple has been close to each other. in weak negligible circuits, from bipolar operating well-controlled the depending V~ and, transistors by a very model to the transistors amplitude “ As a matter of fact, by assuming Cl >> C’z + C3, Cq ~ O and 1?~gHZ~ >> 1, the gain of a single stage of a long chain is found to have the following asymptotic values: low frequency stant transistors parameters controlled of this 81D5 a(vD5 - response two curve, poorly that T7 and the differential Rs a multistage of amplifier (a) common stage are the various 1 15 shows This related CG/CoX Fig. 15. Voltage of MOS They as well. Si-gate could be VITTOZ AND FELLRATH : CMOS ANALOG INTEGRATED CIRCUITS Meanwhile, it must be pointed out that weak inversion operation is fundamentally-limited to low-speed circuits; this is due to the reduced channel conductance for given device 231 [12] [13] dimensions, when ‘compared with strong inversion operation. [14] ACKNOWLEDGMENT The authors wish to thank Dr. M. Dutoit support, E. Vittoz, frequency B. Gerber, and F. Leuenberger, “Silicon%ate CM(X divider for the electronic wrist watch,” IEEE J. SolidSfate Circuits, vol. SC-7, pp. 100-104, Apr. 1972. L. P. Hunter, Handbook of Semiconductor Electronics. New York: McGraw-Hill, 1970, pp. 10-17, K. K. Clarke and D. T. Hess, Communication Circuits: Analysis and Design. Reading, MA: Addison-Wesley, 1971, pp. 636-641. for technological as well as B. Gerber and Dr. M. DarWish for supplying statistical data on devices operating in weak inversion. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] M. B. Barron, “Low level currents in insulated gate field effect Electron., vol. 15, pp. 293-302, Mar. transistors,” Solid-S~ate 1972. R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in low-voltage circuits;’ IEEE J. Solid-State Circuits, vol. SC-7, pp. 146-153, Apr. 1972, R. R. Troutman and S. N. Chakravarti, “Subthreshold characteristics of insulated-gate field%ffect transistors,” IEEE Trans. Circuit Theory, vol. CT-20, pp. 659-665, Nov. 1973. R. J. Van Overstraeten et al., “Inadequacy of the classical theory of the MOS transistor operating in weak inversion,” IEEE Trans. Electron Devices, vol. ED-20, pp. 1150-1153, Dec. 1973, —, “The influence of surface potential fluctuations on the operation of the MOS transistor in weak inversion ,“ IEEE Trans. Electron Devices, vol. ED-20, pp. 1154-1158, Dec. 1973. R. R. Troutman, “Subthreshold design considerations for insulated-gate field-effect transistors,” IEEE J. Solid-State Circuits, vol. SC-9, pp. 55-60, Apr. 1974. “Subthreshold slope for insulated-gate field+ffect transistors,” IEEE Trans. Electron Devices, VOL ED-22, pp. 10491051,Nov. 1975. T. Masuhara er al., VA preeise MOSFET model for low-voltage circuits;’ IEEE Trans. Electron Devices, vol. ED-21, pp. 363371, June 1974. R. W. J. Barker, “SmaJ.1-signal subthreshold model for IGFET’s,” Electron. Let f., vol. 12, pp. 260-262, May 1976. S. M. Sze, Physics of Se?niconducfor Devices. New York: Wiley, 1969, ch. 9. R. J. Van Overstraeten et al., “Theory of the MOS transistor in weak inversion–new method to determine the number of surface states;’ IEEE Trans. Electron Devices, VOL ED-22, pp. 282-288, May 1975. Eric Vittoz (A’63-M’72) was born in Lausanne, Switzerland, on May 9, 1938. He received the M.S. and Ph.D. degrees in electrical engineering from the Federal Institute of Technology, Lausanne, in 1961 and 1969, respectively. After spending one year as a Research Assistant, he joined the Centre Electronique Horloger S.A., Neuch&el, Switzerland, in 1962, where he was involved in micropower integrated circuits development for the watch, while preparing a thesis in the same field. As Associate Director of this Laboratory in charge of the Applications Division, he is now supervising advanced electronic watch developments, with a main inHe also lectures in terest in CMOS digital and analog circuits. integrated-circuit design at the FederaJ Institute of Technology, Lausanne. Jean Fellrath was born in Le Locle. Switzerland. on September 6, 1936. He received the M.S~ degree in electrical engineering from the Ecole Polytechnique de l’Universit& de Lausanne, Lausanne, Switzerland, in 1960. After spending one year as a Research Assistant at the Ecole Polytechnique, one year at Siemens Semiconductors Laboratory in Munich, and three years at the Research Department of the Swiss PTT, he joined the Centre Electronique Horloger S.A., Neucht2itel, Switzerland, in 1965, where he is presently involved with micropower IC’S and watch systems developments. Authorized licensed use limited to: IEEE Xplore. Downloaded on October 20, 2008 at 19:18 from IEEE Xplore. Restrictions apply.