Download So far, we have only considered DC analysis and only resistive drops

Interconnect………..continued
So far, we have only considered DC analysis and only resistive drops! AC analysis due to
di/dt and dv/dt of inductive and capacitive loads has to be taken into account. These are
called Vdd and Ground bounce.
RC Delays
As device sizes decrease the delay of the switching devices decrease, but the delay due to
interconnect keep increasing. This is shown in the figure below.
The length of interconnect is a major parameter affecting delay, usually we try to keep
interconnects as short as possible. A typical interconnects length distribution is shown in
the graph below.
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Lecture#7 Overview
An interconnect is a distributed RC network, with certain time constant that contribute to
delay due to charging and discharging of the entire line every time the input changes.
For simplicity, the entire line usually approximated to a lumped resistor and a capacitor.
Fringing and Parallel plate Capacitances
Interconnect wires are laid over insulators. As such they have capacitances:
Parallel Plate and Fringing. As wire width are scaled down the effect of the fringing
capacitance are becoming dominant.
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Lecture#7 Overview
Ctotal  C p  C f
Parallel Plate Capacitor can be determined as:
W
L
H
C p  C p 0 * W .L
Cp  0
Where, Cp0 is the capacitance per unit area. H is the thickness of the insulator.
The fringing capacitor can be determined empirically using the following relationship:

T
CF   r *

4H
2H
T
ln( 1 
(1  1  ))
T
H
From the picture above, T is the thickness of wire and H is the distance of wire to
substrate.
When dimension of interconnect are large, then the parallel plate component dominates
however as we scale dimensions the fringing component dominates as shown in the graph
below
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Lecture#7 Overview
Cross talk between adjacent metal nets
Crosstalk is the unwanted voltages induced in one conductor from a neighboring
conductor due to capacitive coupling between them,
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Lecture#7 Overview
Cross section view of metal interconnects and associated parasitic
capacitances
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Lecture#7 Overview
Delay of interconnect line
Consider an interconnect line of length L and width W,
Capacitance = C/unit area * L (length) * W (width) = C
Resistance = R/ * number of squares = R
What to do if we need to model the RC line in order to get the delay?
1. Time Constant Analysis
LUMPED MODEL
T-MODEL
 -MODEL
2T-MODEL
2  -MODEL
Similarly, 3T or 3  models can be obtained. As we increase the modeling complexity, a
better approximation of the delay is obtained. Table below gives correlation between
different modeling methods.
Voltage Range
0 – 50%
0 – 63%
10 – 90%
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Lumped RC
0.69RC
RC
2.2RC
Distributed RC
0.38RC
0.5RC
0.9RC
Lecture#7 Overview
Assume R = Resistance per unit length,
C = Capacitance per unit area
The line can be described as a distributed RC network as
From the analysis,
 delay 
rc
N ( N  1) , where N is the number of sections or units. r is the resistance/section
2
and c is the capacitance /section
 delay 
2
rcl
, where l is the length of the interconnect, r is the resistance/unit length and c
2
is the capacitance /unit length.
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Lecture#7 Overview
Interconnect Continued
RC distributed model for interconnect was derived previously as:
 
rc 2
l , where rc is per unit resistance and capacitance
2
rc
0r
  n(n  1)
2
Now for the circuit shown below
What is the maximum practical length that can be used? Let us take an example
Example
A signal is propagated on a 6mm length metal 1 (M1) interconnect, using minimum wire
width. Calculate the delay and comment on methods for reducing this delay.
Delay of wire =
rc 2
l
2
Now the resistance and capacitance of CMOSIS5 are given as (from the manual):
r = 0.07  /
c = 46 aF/µm2, c = 46*1 exp -18, (a = 1 exp -18),
If we normalize the resistance and capacitance to unit length ( assuming our unit length to
be 0.6µ,
r = 0.07  / unit length
c = 46 * 0.36 aF / unit length
0.07 * 4.6 * 0.36 *1018 6000 2

(
) *109 ns
2
0.6
  0.057ns
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Lecture#7 Overview
Is the time constant acceptable? It really depends on the design. If this result is not
acceptable, then we have to solve this problem, by either widening the wire, thus
decreasing the resistance, however that increases the capacitance as well. Now since the
delay is proportional to l2 then a possible solution is to break down the long interconnect
line into smaller segments.
Let us assume, we insert a buffer in the middle of the line,
Using the equation  
rc 2
l
2
0.07 * 4.6 * 0.36 *1018 3000 2

(
) *109 ns
2
0.6
  0.014ns
The overall delay of the two interconnects plus the new buffer is now:
 delayoverall  2 * 0.014   buff
if the buffer has a delay of  buff  0.01ns
 2 * 0.014  0.010
 tot  0.038ns  0.057ns(original  value)
One solution is to insert buffers in the transmission line until the total delay of the line
becomes much smaller than the delay of the buffer.
For the buffer introduced we did minimize the delay. But this one dimensional
minimization, we did mot study its effect on other parameters. . By introducing the
buffer, we have increased the power dissipation, the area and the routing complexities.
When other factors are included, then it is possible to say we can introduce the buffer or
not.
Generally, the maximum length of the wire should be calculated according to the
following criteria.
 buff 
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2 * buff
rc 2
)
l or l  (
rc
2
Lecture#7 Overview
This formula has different values depending on the type of material being used, for
example, the time constant for metal 1 is different from that of poly-silicon.
In case of segmented and unequal interconnects, we usually break down the total length
into multiple paths, each one with their own time constant.
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Lecture#7 Overview
Example
Determine the delay difference if metal 2 was used for interconnect for a signal to
propagated on same length of interconnect, using minimum wire width. Then change
For the same length change the width to1.2 cm and calculate the time.
For Delay use  delay 
rc 2
rc
N ( N  1) ( or
l )
2
2
where N is the number of sections or units.
Do remember that: Small line length: transistor speed governs the circuit speed.
Medium line length Transistor output resistance and line capacitance govern the circuit
speed.
Long line length, line resistance and line capacitance govern the circuit speed.
Cooling the room temperature to 77K reduces the resistivity by an order of magnitude.
At higher frequencies, Ghz and above the skin effect has to be taken into account
Design Guide Lines for high fan-out
Lines with multiple loads will have longer delays.
For lines such as Clocks, Data buses, Control lines
Use wider lines but calculate delay break point
Delay is proportional to l**2 try to avoid long wires if you can, or insert buffers.
Avoid using wider lines if they are long.
Small Geometries
When should the concept of transmission line theory be used?
Whenever the rise time and fall time of a signal is comparable to an interconnect delay,
then the line can be model as a transmission line.
 pd  33  r , with unit of ps/cm
Where,  r is the dielectric constant of the material..
An empirical rule to obtain the critical path delay is:
τpd =1/3 [min (tr, tf )]
if l is the interconnect line length and v is the speed then,
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Lecture#7 Overview
tr,f < 3 (l / v) then use transmission line modeling
tr,f > 5 (l / v) then use lumped model modeling
In between you can use either model.
What is the maximum size of silicon chip?
What is the maximum size of a silicon chip?
Various factors affect the physical size of an integrated chip mainly:





Power dissipation
Packaging
Number of pins
Technology
The interconnect used
The maximum chip size is obtained by
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Lecture#7 Overview
Achip  0.16
RoCo
ln(
RintCint
CINT
Area packaging
 Cl
2
)
Co
Rint, Cint and CINT are resistance and capacitance / per unit length of the interconnect and
the lower and upper case subscript refers to the chip and the package. A is the area of the
die, Co and Ro are the input capacitance and output resistance of a minimum size inverter
and CL is a typical off-chip load.
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Lecture#7 Overview
Inductances
Definition: In electromagnetism, permeability is the degree of magnetization of a material
that responds linearly to an applied magnetic field.
Magnetic permeability Unit: H/m henries per meter.
There exist two types of inductances: Die wires and on-chip inductances.
For die wires,
L
p 4h
ln( )
2
d
Where h is the height of the wire above the substrate,
d is the diameter of the wire and
 pis the magnetic permeability of the material in H/m.
For on-chip,
L
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p 8h w
ln(
 )
2
w 4h
.
Lecture#7 Overview
Example
Determine values for x, y due to inductive and resistive losses when the output driver
sources 10mA in 1.5ns in the following circuit. Assume inductance of the line 13.9
nH/mm
Page 15 of 20
Lecture#7 Overview
From the above circuit, there will be both ground bounce and VDD bounce.
Calculate the total amount of wire inductance
For a wire strip of 1cm, Ltot=13.9*10=139nH
Calculate the voltage drop across the wire
Voltage drop across wire
= 139 *10 9 *
i
t
10 *103
= 139 *10 *
1.5 *109
9
=
139 *10
mv
1.5
= 0.926V
= 926 mV
Assuming that the power supply for the output buffer is 3.3V, we hence have the
following circuit.
At this example we have neglected the resistive drops that usually has to be taken into
account.
Example of ground bounce
So for the above circuit, if the ground is taken to an inverter as shown below:
Page 16 of 20
Lecture#7 Overview
When a ‘1” is applied at the nMOS, while the output is suppose to be ‘0” it might turn on
momentarily because of the spike a voltage of 0.926 appear at the output. The same spike
will propagate through the adjacent circuit. It is also particularly damaging to dynamic
circuit. Also it will alter the VSB and that will have an effect on speed and current drive
capability of the inverter.
How to avoid this problem?
The 1cm length wire is not practical in today’s technology. We now also use tens or
hundreds of VDD and GND pads. As a result, the distance of 1 cm is very impractical.
More realistic distances are 1mm and less. Also the assumed inductance is too high and is
not practical.
How about when we drive several buffers at the same time? This is very possible, as
buses are getting wider, as well as the current demand increases several folds while it has
to be delivered in shorter time, thus the ground bounce and VDD bounce is increased.
Always calculate GND bounce and VDD bounce when distributing power lines!
Design Guidelines
Add .01microF decoupling capacitors on the supply lines.
Put simultaneously switching output/input lines next to power lines or just sandwich
them. Other techniques include:
Using a Flip Chip device packages
Reduce slew rate
Limit the number of simultaneously switching output.
Spread out simultaneously switching outputs, SSOs
Use Out-of-phase simultaneously switching output (SSOs) using phase-locked
loops (PLLs)
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Lecture#7 Overview
Example
What will be the power line width if you drive a 10pF load at 1GHz
Assume Vdd=3.5V.
Solution
The required power is
P = fVDD2CL
9
= 1*10 * (3.5)
= 0.1Watt
2
*10 *1012
P=I*V
I = 0.1/3.5
I ≈ 30mA
If we use a conductor with current density J = 1mA / um, we will need a width of 30um
At this point, we need to go back and re-do the calculation for the inductance with the
new width & length parameters.
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Lecture#7 Overview
Charge Sharing
Consider a bus circuit with the following structure
Qb = CbVb, where Qb is charge on the bus, Cb is the bus capacitance and Vb is the voltage
at the bus.
Similarly, for the charge on the signal line, we have
Qs=CsVs, where Qs is charge on the signal line, Cs is the signal line capacitance and Vs is
the voltage present on the signal line.
When the NMOS transistor switches on, charge sharing occurs between the bus and the
signal line.
The net charge of the two lines combine becomes
QR = CRVR, where VR is the resulting voltage of the bus and the signal.
VR = QR /CR
VR 
CbVb  CsVs
Cs  Cb
Consider one scenario
Let, Vb = 3.3 Volt representing logic ‘1’ and Vs = 0V representing logic ‘0’
According to charge sharing, VR 
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CbVb  CsVs
Cs  Cb
Lecture#7 Overview
VR 
3.3Cb
C s  Cb
VR 
3.3
 1.7V
2
This is under the assumption that Cs and Cb are equal, and the resulting VR is
unacceptable!
How to remedy this problem:
Hence we must have the bus capacitance Cb >> Cs
Example
Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances.
Assume bus capacitance to be 10pF.
VDD * Cb
C s  Cb
3.3 *10 pF
VR 
10  (64 * 0.1 pF )
VR 
VR 
33
16.4
VR  2V
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Lecture#7 Overview