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Patricia Gonzalez Divya Akella VLSI Class Project Motivation : Sub-threshold Operation Sub-threshold processor which runs on 180mV [1] Sub-threshold FPGAs A sub-VT ring oscillator at 80mV [2]. A 65nm chip : 256kb memory in sub-threshold region to below 400mV [3] New wireless applications : Wearable body sensor node (19uW) running on harvested energy – small devices, long lifetimes! Ultimate aim ? Reduce Power consumption! Variation In sub-threshold Issue : Meet Throughput 100 operations every 5 seconds -> Frequency requirement Taken from [1] B. Calhoun Motivation : Yield a critical obstacle : sensitivity of sub-threshold circuits to variations in process, voltage, and temperature (PVT) Affects delay : limits product yield ! A system that adjusts the chip operation to account for PVT ? Motivation : Razor • System should be able to run at multiple frequencies and voltages. • Design to ensure correct operation at all PVT variations. • Variations ? Environmental, local, global, voltage droops, even data dependent! • Razor approach : DVS based on dynamic detection of errors Motivation : PDVS • Voltage reduced to minimum voltage possible. • Headers allow to dither between voltages. • Different energies for different modes of operation/workload! The Problem • First “high” input is caught by the flop : seen at output Q • Second “high” input is missed ? Test circuit • To experiment with this problem : chose a 3 bit adder • Output is shown to be flopped Solution • Shadow latch • Error comparator Waveform System Overhead ? • Power consumption of razor circuit : Worst case (FF) corner power at 0.4 V = 1.4 nW Further optimization is definitely possible! • Use of razor circuit only for critical paths Design • • • • Typically – corner analysis to select a supply voltage ? Extra margin for worst case scenario! What if variability is rare , what if it never occurs ? In lower processes and sub – threshold , variability might be so much – voltage margins go up! • Optimization during circuit design can now be done for a typical case • We attempt to show use of razor in sub-threshold voltages. Savings example (T = 20C) V (3 freq of operation) % savings 0.4 0.425 0.45 0.475 31.81% 21.99% 14.21% 0.5 0.55 0.6 0.65 38.21% 25.49% 18.32% 0.7 0.8 0.9 1 42.49% 29.24% 15.08% A Perspective of Yield • Variable voltage and frequency to adjust to variation • It will improve the efficiency, thereby increasing yield and lowering costs. • Achievable performance for a given energy budget • Improve yield at a given frequency by allowing slower chips to speed up by going to higher VDD Yield against process variation !! T = 27ºC T =20 ºC 0.7 V 0.8 V 0.9 V 34% 1V 0.7 V 36% 0.8 V 0.9 V T = 100ºC 1V 0.7 V 0.9 V 45% 1% 40 MHz 32% 18% 12% 18% T=20ºC 0.5 V 1V 22% 33% 39% 0.8 V 0.55 V 10% T=27ºC 0.6 V 0.65 V 0.5 V 0.55 V 0.6 V T=100ºC 0.65 V 0.5 V 0.55 V 0.6 V 0.65 V 0% 0% 11% 17% 200 kHz 50% 24% 61% 9% 11% T=20ºC 0.4 V 0.43 V 39% 48% 30% 0.45 V T=27ºC 0.48 V 0.4 V 0.43 V 0.45 V T=100ºC 0.48 V 0.4 V 0.43 V 0.45 V 5% 3% 9% 15% 30% 100 kHz 25% 32% 35% 36% 30% 58% 23% 0.48 V References [1] Wang, A.; Chandrakasan, A.; , "A 180mV FFT processor using subthreshold circuit techniques," Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International , vol., no., pp. 292- 529 Vol.1, 15-19 Feb. 2004 2] B. H. Calhoun and A. Chandrakasan, “Characterizing andModeling Minimum Energy Operation for Subthreshold Circuits,” in ISLPED, 2004, pp. 90–95. [3] B. Zhai, et al., “Theoretical and Practical Limits of Dynamic Voltage Scaling,” in DAC, 2004, pp. 868–873. [4] Dan Ernst, Tao Phan. Razor : A low power pipeline based on Circuit Level timming speculation. [5] Mathias Eireiner,. In situ Delay Characterization and Local Supply voltage adjustment for compensation of local parameter variations. Gate leakage based timer : • • • • • Intended to use it as a clock source Did not integrate into the system Originally, used as a timer in the sub – Hz range Gate leakage based system – variation with temperature is reduced Found that with varying capacitance charging time, leakage transistors and Schmitt trigger design – higher frequency ranges can be obtained. Voltage Time period 0.4 3.71E-07 0.5 5.65E-08 0.6 1.40E-08 0.7 5.16E-09 0.8 2.54E-09 0.9 1.54E-09 Frequency 2.70E+06 1.77E+07 7.16E+07 1.94E+08 3.94E+08 6.48E+08 Can be used as an unstable source of clock on chip, with possible caliberation with a stable clock source.