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Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Design of an Input Multiplexer for Video
Applications
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Pavel Angelov
LiTH-ISY-EX--10/4411--SE
Linköping 2010
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
Design of an Input Multiplexer for Video
Applications
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Pavel Angelov
LiTH-ISY-EX--10/4411--SE
Handledare:
J Jacob Wikner
isy, Linköpings universitet
Examinator:
J Jacob Wikner
isy, Linköpings universitet
Linköping, 11 June, 2010
Avdelning, Institution
Division, Department
Datum
Date
Division of Electronics Systems
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Språk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
Övrig rapport
2010-06-11
—
LiTH-ISY-EX--10/4411--SE
Serietitel och serienummer ISSN
Title of series, numbering
—
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-65530
Titel
Title
Konstruktion av en Ingångsmultiplexer för Videotillämpningar
Design of an Input Multiplexer for Video Applications
Författare Pavel Angelov
Author
Sammanfattning
Abstract
In modern home entertainment video systems the digital interconnection between
the different components is becoming increasingly common. However, analog signal sources are still in widespread use and must be supported by new devices.
In order to keep costs down, the digital and the analog receiver chains are implemented on a single die to form a system-on-chip (SoC). For such integrated circuits,
it is beneficial to reduce the number of power supply domains to a minimum and
preferably use the core voltage to power the analog circuits.
An eight-to-one input multiplexer, targeted for video digitizer applications,
is presented. Together with the multiplexer, a simple current-mode DC restoration circuit is provided. The goal has been to design the circuits for a standard,
single-well, 65 nm CMOS process, entirely using low-voltage core transistors and
a single 1.1 V supply domain, while allowing the input signal voltages to extend
beyond the supply rails.
To fulfill the requirements, a bootstrap technique has been proposed for the
implementation of the multiplexer switches. Bootstrapping a CMOS switch allows
high linearity, as well as wide bandwidth and dynamic range, to be achieved with
a very low supply voltage. The simulated performance is: 3-dB bandwidth of
536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of
65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistor
is stressed by high voltages, therefore, the circuit reliability is guaranteed. The
DC restoration circuit utilizes the main video ADC, for measuring the DC level,
and is capable of setting it with an accuracy of 60 µV within the range of 100 mV
to 500 mV.
Nyckelord
Keywords
analog video, AFE, bootstrap, analog multiplexer, analog switch, leakage current,
DC restoration, DC clamp, sub-micron CMOS
Abstract
In modern home entertainment video systems the digital interconnection between
the different components is becoming increasingly common. However, analog signal sources are still in widespread use and must be supported by new devices.
In order to keep costs down, the digital and the analog receiver chains are implemented on a single die to form a system-on-chip (SoC). For such integrated circuits,
it is beneficial to reduce the number of power supply domains to a minimum and
preferably use the core voltage to power the analog circuits.
An eight-to-one input multiplexer, targeted for video digitizer applications,
is presented. Together with the multiplexer, a simple current-mode DC restoration circuit is provided. The goal has been to design the circuits for a standard,
single-well, 65 nm CMOS process, entirely using low-voltage core transistors and
a single 1.1 V supply domain, while allowing the input signal voltages to extend
beyond the supply rails.
To fulfill the requirements, a bootstrap technique has been proposed for the
implementation of the multiplexer switches. Bootstrapping a CMOS switch allows
high linearity, as well as wide bandwidth and dynamic range, to be achieved with
a very low supply voltage. The simulated performance is: 3-dB bandwidth of
536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of
65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistor
is stressed by high voltages, therefore, the circuit reliability is guaranteed. The
DC restoration circuit utilizes the main video ADC, for measuring the DC level,
and is capable of setting it with an accuracy of 60 µV within the range of 100 mV
to 500 mV.
v
Acknowledgments
The person who deserves most gratitude for the completion of this thesis work
is my supervisor and examiner Dr. J Jacob Wikner, he has provided me with
the opportunity to prepare my thesis work in the division of Electronics Systems.
Work and discussions with him have always been inspiring and highly motivating. Dr. Wikner, you have guided me through the thesis work in a superb fashion. Thanks!
I am also thankful to Joakim Alvbrant for the help with the tools, and to everybody who worked in the mixed-signal thesis group, for the general discussions and
support. Thanks also go to Yasir Ali Shah for opposing at the thesis presentation
and providing valuable feedback for this report.
I am thankful to my friend Martin Tapankov for suggesting many corrections
and improvements to the text and formating of this report, as well as for the
numerous technical discussions.
I thank my girlfriend and life partner Valentina for the support and for the
love, she also helped reviewing and proof-reading the final text of this report.
I owe never-ending gratitude to my parents who have always supported me
unconditionally and for loving me. Without you none of this would have been
possible. Thank you!
vii
Contents
1 Introduction
1.1 Purpose and goals . . . . . . . . . . . . . . . .
1.2 Project scope . . . . . . . . . . . . . . . . . . .
1.3 Target CMOS process description and features
1.4 Video digitizer overview . . . . . . . . . . . . .
1.5 Analog video signals . . . . . . . . . . . . . . .
1.5.1 Monochrome video . . . . . . . . . . . .
1.5.2 Color video . . . . . . . . . . . . . . . .
1.5.3 Voltage levels . . . . . . . . . . . . . . .
1.5.4 Signal coupling and termination . . . .
2 Analog Multiplexers and Switches
2.1 Introduction . . . . . . . . . . . . . . .
2.2 The MOS transistor as a switch . . . .
2.2.1 Transmission gate . . . . . . .
2.2.2 Bootstrapping techniques . . .
2.3 The implemented analog switch . . . .
2.3.1 Bootstrapped switch—principle
3 DC
3.1
3.2
3.3
3.4
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restore block
The need for DC restoration . . . . . . . . . . . .
Voltage-mode DC clamp . . . . . . . . . . . . . .
Current-mode DC clamp with current sources . .
Current-mode DC clamp without current sources
3.4.1 The implemented DC clamp . . . . . . . .
4 Analog Multiplexer - performance metrics
4.1 Bandwidth . . . . . . . . . . . . . . . . . .
4.2 Linearity . . . . . . . . . . . . . . . . . . . .
4.3 Inter-channel isolation . . . . . . . . . . . .
4.4 Clamp circuit performance metrics . . . . .
4.5 Leakage and lower cut-off frequency . . . .
ix
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x
5 Design Details
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . .
5.2 Bootstrapped switch . . . . . . . . . . . . . . . . .
5.2.1 Special design considerations . . . . . . . .
5.2.2 Switch linearity and bandwidth . . . . . . .
5.2.3 Bootstrap charge retention . . . . . . . . .
5.2.4 OFF-state resistance and isolation . . . . .
5.3 DC restoration circuit . . . . . . . . . . . . . . . .
5.3.1 Control signals and actual implementation .
5.4 Multiplexer topology and top-level design . . . . .
5.4.1 Design considerations and transistor sizing
Contents
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6 Test bench and simulation results
6.1 Test bench design . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Simulated performance parameters and results . . . . . . . . . . .
6.2.1 Internal voltage levels . . . . . . . . . . . . . . . . . . . . .
51
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53
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7 Conclusion
57
8 Future work
59
Bibliography
61
A VerilogA code of the binary-to-thermomenter encoder
63
B VerilogA code of the video signal generator
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List of Figures
1.1
1.2
1.3
1.4
Block diagram of the video analog-front-end
Electron beam scanning on a CRT screen. .
Analog video signal . . . . . . . . . . . . . .
AC coupling of an analog video signal. . . .
integrated
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2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Functional diagram of an analog multiplexer. . . . . . .
Model of a real closed switch with parasitic elements. . .
A single transistor analog switch. . . . . . . . . . . . . .
Transmission gate realization of an analog switch. . . . .
Transmission gate on-resistance . . . . . . . . . . . . . .
Conceptual schematic of a bootstrapped switch. . . . . .
Detailed schematic of the bootstrapped switch presented
Topological diagram of the bootstrapped switch . . . . .
Bootstrapped switch clocks . . . . . . . . . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
AC coupling signal effects . . . . . . . . . . .
AC coupling with DC restoration. . . . . . .
Voltage-mode DC restoration. . . . . . . . . .
Current-mode DC restoration. . . . . . . . . .
Current-mode clamp closed-loop . . . . . . .
Realization of the controlable current source.
4.1
4.2
4.3
4.4
Effect
Effect
Effect
Effect
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Bootstrapped switch—original schematic . . . .
Bootstrapped switch—Harmful input current .
Bootstrapped switch—final schematic . . . . .
Bootstrapped switch—non-linear capacitances .
Bootstrap leakage currents . . . . . . . . . . .
T-switch arrangement . . . . . . . . . . . . . .
5-bit charge pump . . . . . . . . . . . . . . . .
The DC restore circuit as a digital control loop
Clamp charge pump transfer characteristic . . .
Multiplexer switch final . . . . . . . . . . . . .
Multiplexer—final architecture . . . . . . . . .
6.1
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bandwidth limitation of the video signal. . . . . . .
non-linear distortion of the video signal. . . . . . . .
unstable DC clamp. The brightness is varied by 5%.
leakage current through the input capacitor. . . . .
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Complete Multiplexer test bench . . . . . . . . . . . . . . . . . . .
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in [2]
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2
Contents
List of Tables
1.1
1.2
Available CMOS transistors . . . . . . . . . . . . . . . . . . . . . .
Video voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . .
5
9
6.1
6.2
Simulated performance parameters . . . . . . . . . . . . . . . . . .
Simulated stress results . . . . . . . . . . . . . . . . . . . . . . . .
54
55
Chapter 1
Introduction
The objective of this thesis is to design an input analog multiplexer to be used in
video digitizer applications and in a video analog-front-end integrated circuit (AFE
IC) designed at the division of Electronics Systems, Linköping University. The
design must be implemented in a low-voltage, “digital” CMOS process with as
many components as possible brought down to layout level.
The multiplexer, designed in this thesis work, is an 8-to-1 multiplexer incorporating a DC restoration circuit (clamp) for setting the DC level of the incoming video signal. The key performance measures are high linearity (more than
60 dB at 20 MHz), high bandwidth (more than 500 MHz) and low crosstalk (less
than -70 dBc).
With the development of digital electronics, “digital” video formats, like DVI,
HDMI and even video-over-USB, are becoming increasingly widespread. However,
due to their historical usage, the analog video signaling formats are supproted
by virtually all video devices in use today. Many digital devices, like personal
computers, home entertainment video systems, TV sets, and even some photo
cameras and MP3 players, support only analog video signaling. This means that
in new devices analog video support must be availabe in parallel with the digital
formats. In today’s highly integrated systems it is absolutely necessary to have
the functionality for both analog and digital video formats on the same chip.
Therefore, to take advantage of the modern CMOS processes, the analog parts
must be designed using unconventional techniques, thus avoiding the problems
introduced by the deep sub-micron CMOS technologies.
1.1
Purpose and goals
The following goals and tasks were set as guidelines for the project execution:
• Design and verify a multiplexer together with a DC restoration circuit, as
well as an analog filter for limiting the bandwidth of the low-resolution video
formats. Cover the performance requirements defined in the project design
specifications.
3
4
Introduction
• Aim the design towards applications with low supply voltage and low power
consumption, possibly operated from a battery.
• Use digital circuit techniques as much as possible in order to facilitate scalability with future CMOS technologies and to make the realization in submicron CMOS processes feasible.
• Design the components such that as many as possible analog video formats
are supported in the final digitizer integrated circuit.
1.2
Project scope
Even though the project is aimed at designing a fully functional video multiplexer
it is not concerned with the implementation of the accompanying digital control
blocks. The intention is to provide those parts of the multiplexer that directly
interact with the analog signals, but leave the control strategy open for further
development. However, some of the interfacing digital logic is provided, but it
should not be considered optimal.
The project implementation is limited by the constraints that the video AFE
has, in terms of IC manufacturing process, available power supply, supported
video formats and design specifications and goals. The actual specifications will
be discussed later in the appropriate chapters.
1.3
Target CMOS process description and features
The semiconductor process, that the video AFE is designed in, is a state-of-the-art
65 nm, n-well process with seven metal and one poly layers.
The process provides a multitude of devices. There are two major transistor
types—high-voltage, thick-oxide MOS transistors for a nominal supply voltage of
2.5 V, and low-voltage, thin oxide MOS transistors for a nominal supply voltage
of 1.1 V. The two transistor types have two flavors each—general purpose (gp),
and low power (lp). The low power transistors have thicker gate oxides to provide
low gate leakage currents for non-speed critical circuit parts. The transistors
have three threshold voltage options - high, standard and low Vt . The available
transistors with their main features are summarized in table 1.1.
As the design of the chip is targeted towards low power supply voltages and
low power consumption only low voltage devices are used. This also lowers the
cost since separate manufacturing steps are required for the high and low voltage
devices.
1.4
Video digitizer overview
The designed multiplexer is a part of a large integrated circuit, a video digitizing device, where it is used to select the active analog input. Since the digitizer
1.5 Analog video signals
Transistor
designation
hvtlp
svtlp
lvtlp
hvtgp
svtgp
lvtlgp
5
Description
Gate leakage
high-Vt ,
low power
standard-Vt ,
low power
low-Vt ,
low power
high-Vt ,
general purpose
standard-Vt ,
general purpose
low-Vt ,
general purpose
low
Drain-Source
leakage
low
low
medium
low
high
high
low
high
medium
high
high
Table 1.1: Transistor types available from the target CMOS technology
stands at the boundary of the analog and digital domains it is also termed analogfront-end (AFE). The architecture of the video AFE is shown in figure 1.1 and is
separated in two major blocks. The digitizing channel consists of an input multiplexer together with a DC restoration circuit, a low-pass filter, a programable
gain amplifier (PGA) and an analog-to-digital converter (ADC) which digitizes
the video signal. This is followed by a digital post-processing block which performs gain and error correction. In order to cover all supported video formats five
digitizing channels are used in parallel.
The timing block processes the synchronization information in the video signal
(either embedded sync pulses or separate synchronization signal) and extracts the
timing information needed to control the digitizing channel. The input signal is
fed to a multiplexer, which selects the source of the synchronization signal, then
to a phase-locked-loop (PLL) which aligns its output to the input synchronization
signal, but at a higher frequency corresponding to the pixel rate. The delaylocked-loop (DLL) is used to time-shift the rising edge of the clock produced by
the PLL so that the position at which the video signal is sampled can be precisely
controlled and selected, thus allowing under-sampling to be utilized.
The AFE also incorporates a digital control block, which programs the operation of the different parts: video input and sync input selection, PGA gain,
PLL multiplication factor and DLL phase. The video multiplexer, in particular,
receives control signals for input selection, clamp activation and clamp voltage.
1.5
Analog video signals
Originally analog video was designed for the monochrome broadcast TV. The
cathode-ray-tube (CRT) was the only device available for video output in the
early TV sets, so the video signal format was, naturally, meant for display on
6
Introduction
5 x DIGITIZING CHANNEL
Multiplexer
Designed blocks
Filter
PGA
Bias
ADC Reference
Generator
Main
Video
ADC
Digital signal
processing
Gain correction
Offset correction
Sag
compensation/Clamp
Control
Clamp
Slicer
Slicer
Multiplexer
2 x TIME/REF
CHANNEL
PLL
DLL
DLL
Digital signal
processing
Sync detection
Clock dividers
Registers
DLL
Bandgap reference
Current and volatge reference
27-MHz Oscillator
(RC type)
Power-on reset (POR)
Figure 1.1: Block diagram of the video analog-front-end integrated circuit.
a CRT screen. This largely determines what “features” the analog video signal
incorporates.
1.5.1
Monochrome video
The image on a CRT is formed by sweeping an electron beam over the back surface
of the screen [1], starting from the top-left corner and continuing, line by line, to
the botom end. After drawing a complete line, the electron beam is “swept” back
to the left to start drawing the next line. After a whole frame has been drawn the
beam is swept to the top-left corner and the display of the next frame begins. This
process is shown in figure 1.2. The sweeping of the beam to the left and to the top
is called horizontal and vertical retrace, respectively. Actually, to save bandwidth,
in the TV formats the image is not displayed progressively, line-by-line, but is
instead scanned odd lines first and then, on the next vertical retrace—even lines,
this is called interlaced video.
1.5 Analog video signals
7
The tracing motion of the electron beam is controlled by the video signal. A
portion of a signal representing one line of video is shown in figure 1.3. The horizontal scan starts slightly outside the visible area of the screen, this corresponds
to the part of the video signal, called back porch, where the signal is kept at a level
Front Porch
Back Porch
Horizontal retrace path
Active Video
Vertical retrace path
Scan lines
Active Video
Figure 1.2: Electron beam scanning on a CRT screen.
100%
High detail
region
Amplitude
75%
50%
Next line
25%
0%
Sync
pulse
Back porch
Blanking
pulse
Front porch
Time
Figure 1.3: Analog video signal representing one line of a monochrome video frame.
8
Introduction
corresponding to the color black. After that the actual image line is displayed, this
portion of the signal is called active video. The voltage of the active video portion
of the signal carries the color and brightness information of the pixel corresponding
to the position of the beam at the particular instant of time. At the end of the
line the signal is again blanked (brought to a level corresponding to black) and
the beam is brought out of the visible screen area. This part of the video signal is
called front porch. The horizontal retrace is controlled by a very important part of
the video signal, following the front porch—the horizontal synchronization (hsync)
pulse. During the hsync pulse the beam is brought back to its initial position, at
the left of the screen and then released to display the next line. The length of the
hsync pulse is long enough so as to allow the CRT control circuitry to settle. The
voltage level of the sync pulse corresponds to a blacker-than-black color, so that
the retrace period is not visible on the screen.
After the whole image is displayed, a pulse similar to the hsync pulse, called
vertical synchronization, or vsync pulse occurs in the video signal and the beam
is returned to the top left corner of the screen.
1.5.2
Color video
So far, we have only discussed the case where just a singel color is to be displayed.
In order to represent color video three separate signals are required—one for red,
one for green and one for blue, or RGB. These three base colors are combined
on the screen to form the original colors of the image. Despite of that, the basic
principle of drawing the image on the screen remains the same.
The need of three separate colors means that three times the number of cables,
or three times the bandwidth, of the monochrome signal are required to transmit
color video. To solve this problem several signaling (RGB, Y Pb Pr , composite) and
encoding (PAL, SECAM and NTSC) techniques were developed to represent the
colors so that less cables/bandwidth are needed. However, any operation on the
original RGB video signal deteriorates the image quality.
The first step in limiting the bandwidth is the color difference representation of
the original RGB signal. This is merely a transformed color space called Y Pb Pr .
It is again formed by three signals, the luma Y carries the brightness (the mean
value of the red, green, and blue), PB is the difference between the original blue
and luma, and PR is the difference between the original red and luma. The green
color can then be derived from the recovered blue and red and the original luma
signals. The Y Pb Pr still requires three cables to send the video, but due to the
properties of the human eye, which is more sensitive to variations in brightness
than to variations in color, the color signals can be filtered to half the bandwidth
of the luma signal. The synchronization and blanking information is overlaid on
top of the luma signal.
To limit the required number of wires, the color difference signals are used
to modulate a color subcarrier, the resulting signal is called chrominance. This
reduces the required number of wires to just two: one for luma and one for chrominance. This type of video signaling is called S-Video. The luma and chroma signals
can be combined into just one signal to form a signal called composite video, which
1.5 Analog video signals
Video format
RGB
RGB sync–on–green
Y Pb Pr
luma
chroma
(PAL)
Y Pb Pr
luma
chroma
(NTSC)
S-video
luma
chroma
(PAL)
S-video
luma
chroma
(NTSC)
Composite video (PAL)
Composite video (NTSC)
9
Active video
700 mV
700 mV
700 mV
700 mV
714 mV
1009 mV
700 mV
885.1 mV
714 mV
835 mV
933.85 mV
934.15 mV
Sync
–
-300 mV
-300 mV
–
-286 mV
–
-300 mV
–
-286 mV
–
-300 mV
-286 mV
Peak amplitude
700 mV
1V
1V
700 mV
1V
1.009 V
1V
885.1 V
1V
0.835 V
1.234 V
1.220 V
Table 1.2: Voltage levels for the different video formats. Blanking level is assumed
to be 0 V in all cases.
is used in terrestrial television broadcast and in home video entertainment systems.
The more the original RGB signal is processed the more quality and resolution
is lost. This is the reason why different video systems stop processing the signal
at different stages. Computer graphics and some high quality home entertainment
systems directly use the RGB or Y Pb Pr (also called component) video signals.
S-video and component video are used in TV sets, DVD players, set-top boxes,
etc.
1.5.3
Voltage levels
The information in the analog video is carried both in the value and in the time/position of the signal. For PC graphics systems, using RGB signaling, the peakto-peak voltage level is defined to be either 0.7 Vp-p , when the sync is a separate
signal, or 1 Vp-p when the sync is embedded in the green signal (termed syncon-green). Since the input multiplexer is only required to preserve the signal, the
details of the voltage levels of the different parts of the video signal for the other
video formats and encoding techniques are not of a particular interest for the design of the video multiplexer. What is important are the maximum peak-to-peak
voltages that occur and the video blanking level. Table 1.2 lists these parameters
for the different video signaling and encoding formats.
As the video AFE is targeted towards low-voltage design, the power supply
voltage available for the input multiplexer is specified to be only 1.1 V, meaning
that the signal levels that are to be switched are actually higher than the supply
voltage. It is a major challenge to handle signals larger than the supply voltage
in CMOS circuits and proved to be the main problem in designing the video
multiplexer circuitry.
10
1.5.4
Introduction
Signal coupling and termination
Video signals can be both DC or AC coupled between devices. DC coupling
means that the input DC level of the receiving device is defined by the output of
the previous device. This means that the two devices must be designed to operate
with the same common-mode level and that the ground reference be kept at the
same potential at both ends. The existence of DC path means that dangerous DC
currents may flow between devices powered by different power supplies. This is
the case, for example, in a home entertainment system where the TV set and the
set-top box are powered separately. DC coupling is usually utilized within one and
the same system where the common-mode levels are well defined.
Systems, designed to accept signals from different sources, must be AC coupled
so that the common-mode level of the receiving end is well defined. To stop the
DC component, a capacitor is placed in series with the signal path, as illustrated
by figure 1.4. Thus, in order to achieve optimal performance, the two devices can
set their own common-mode level at both sides of the input capacitor.
−
+
DC
Clamp
On-chip
Sending device
Receiving device
Figure 1.4: AC coupling of an analog video signal.
AC coupling introduces some problems as well. The receiving end must provide
the means of setting the DC level at its input, leading to an increase of the required
die area due to the additional circuitry. Since the video signal bandwidth extends
to very low frequencies (the vsync frequency is at the order of 60 Hz), hence,
in order to preserve the integrity of the signal, the coupling must not introduce
significant attenuation. If the input resistance seen at the receiving device, after
the input capacitor, is too low, the voltage on the capacitor will tend to track
the mean level of the video signal. This effect (termed sag) causes variations of
the brightness level at different parts of the picture. Circuits used for setting the
DC level are called DC restoration, or DC clamp circuits. The clamp is, usually,
activated only during the sync pulses or part of the back porch, so that the change
in signal level is not visible on the screen.
Video signals are usually sent over 75–Ω cables, which are terminated at both
ends to avoid reflections. To save board space, some low-cost manufacturers do
not provide the termination at the receiving end, this causes the voltage levels,
1.5 Analog video signals
11
seen at the input, to double. A non-mandatory design requirement, to support
double input levels, has been put for the input multiplexer, so this also has been
investigated during the design process.
Chapter 2
Analog Multiplexers and
Switches
2.1
Introduction
The main objective of this thesis is to design an analog multiplexer—a device used
to select one-out-of-n inputs. Analog here refers to the continuous nature of the
input signals that are to be switched/processed, not to the actual implementation
of the internal schematics of the multiplexer.
Vin1
Vin2
S2
S3
Vout
Vin3
S1
VinN
Sn
Figure 2.1: Functional diagram of an analog multiplexer.
The functional diagram of an analog multiplexer is shown on figure 2.1. It is
composed of n switches with one of their terminals connected together and serving
as an output of the multiplexer, while the other terminal—serving as an input. At
any instant of time only one of the switches Si is closed, while the rest are open.
The output voltage is, thus, equal to the voltage at the input corresponding to
the closed switch, while the signals on the inputs with their switches open, ideally
13
14
Analog Multiplexers and Switches
have no effect on the output signal.
Obviously, the main building block of an analog multiplexer is the analog
switch, thus its performance largely determines the performance of the multiplexer as a whole. Ideally, when closed (on-state), the switch should present a
short-circuit and when open—infinite impedance. In practice, however, this is not
the case and the switches present (small) resistance when on and a small current
flows through the switches that are open (off-state). Furthermore, there exists
capacitance present between the two terminals of the switch (shunt capacitance)
and between each terminal and ground, this is shown on figure 2.2. The output
capacitance, combined with the finite on-state resistance, limits the bandwidth of
the switch, while the shunt capacitance deteriorates the off-state isolation at high
frequencies.
Cshunt
Cin
Ron
Cout
Vout
Vin
S1
Real Switch
Figure 2.2: Model of a real closed switch with parasitic elements.
Due to the analog nature of the video signals, it is of primary importance that
the multiplexer does not introduce non-linear distortion. This is especially true for
analog video where the color and brightness information are stored in the signal
amplitude. In a practical CMOS implementation of a multiplexer, the main source
of non-linearity is the dependence of the on-state resistance on the input voltage.
Therefore; most of the multiplexer design time was devoted in achieving linear
(enough) behavior of the switches.
It must also be noted that the switching speed between the different inputs
does not need to be done with high speed, nor is the switching required to be
glitch-free.
2.2
The MOS transistor as a switch
There are several approaches to implement analog switching behavior in a CMOS
circuit. It is possible, for example, to turn off the bias current of an amplifier, effectively stopping the propagation of the input signal to the output. This approach
is, however, considered too analog and was not investigated further.
The simplest electronic switch, that can be implemented in CMOS technology,
is a single MOS transistor, with the drain and source terminals acting as the two
2.2 The MOS transistor as a switch
15
Vout
Vin
Vout
Vin
Vcontrol
terminals of the switch and the gate as the control input. This arrangement is
shown on figure 2.3, where an NMOS transistor has been chosen. From basic
Figure 2.3: A single transistor analog switch.
device physics, it is known that the first order approximation of the drain current
of a NMOS transistor, operating in linear region with VDS < (VGS − VT H ), is:
ID ≈ µn Cox
W
(VGS − VT H )VDS
L
(2.1)
That is, if the gate voltage is kept constant, the drain current varies linearly
with the source (input) voltage. This represents a non-linear resistance seen in
the signal path, and hence causes significant distortion. Furthermore, if the input
voltage becomes higher than VG − VT H the transistor cuts off and the output
waveform is clipped. This limits the available input signal range and makes the
circuit particularly unsuitable for low-voltage CMOS technology implementation.
For our design case the gate can be kept at the supply voltage of 1.1 V and since
the threshold voltage of the transistors is about 250 mV the usefull signal range is
limited to about 750 mV. A rather small value, only suitable for the low voltage
swing signals like RGB .
2.2.1
Transmission gate
A significant improvement over the single transistor switch can be achieved by connecting two transistors with different conductivity (NMOS and PMOS) in parallel,
this is shown on figure 2.4. The dependace of the on-state resistance of the two
transistors on the input voltage is approximately the same, but with an opposite
sign. That is, when the input voltage increases the NMOS resistance increases
while the PMOS resistance decreases and vice versa. Also, when one of the transistors enters the cut-off region the other one continues to conduct, significantly
extending the useful signal range of the circuit. The variation of the resistance for
both transistors as well as the combined resistance of the parallel connection as a
function of the input voltage is illustrated in figure 2.5. It is seen that the total
resistance of the switches remains approximately constant.
Analog Multiplexers and Switches
Vout
Vin
Vin
Vout
Vcontrol
16
Figure 2.4: Transmission gate realization of an analog switch.
RON
NMOS
PMOS
Resistance
of the parallel
combination
-
Signal Voltage
+
Figure 2.5: Dependence of the on-resistance of MOS transistors and their parallel
combination on the applied gate-source voltage.
2.2 The MOS transistor as a switch
17
The smallest resistance variation is achieved when the PMOS transistor is sized
such that the electrical size of the two transistors is approximately the same. Such
matching, however, is difficult to achieve in sub-micron CMOS technologies, which
are characterized with significant device variations, hence large non-linear distortions would occur across process corners. Furthermore device matching techniques
are considered to be too “analog” and therefore do not fit well within the “digital”
design philosophy adopted for this project.
2.2.2
Bootstrapping techniques
We have seen that the main source of non-linearity of the transistor switches comes
from the variation of the on-resistance caused by the variation of the gate-source
voltage. Bootstrapping is a technique with which the gate-source voltage is kept
approximately constant throughout the voltage range of the input signal. This
is achieved by connecting a pre-charged capacitor (termed bootstrap capacitor)
between the gate and source terminals of the pass transistor. The bootstrap capacitor is pre-charged to the supply voltage during the off-state and then connected
to the pass transistor through a separate set of switches. With this arrangement
the gate voltage follows the source voltage with a DC offset equal to the capacitor
voltage. Figure 2.6 shows the concept of the bootstrapping technique. The switch
is turned off by simply connecting the gate of the main switch to ground.
Vboot
Pass
Transistor
Vout
Vin
Cboot
Figure 2.6: Conceptual schematic of a bootstrapped switch.
Bootstrapping the gate of the switch transistor largely eliminates the variation
of the on-resistance due to variation of the gate-source voltage. However, due to
the body effect the on-resistance still depends on the source voltage. This effect can
be compensated by bootstrapping the bulk of the pass-through transistor as well.
However, for a typical CMOS process, the bulk terminals of NMOS transistors are
not separately accessible, therefore, PMOS devices must be used instead. Circuits
that compensate for the body effect by bootstrapping the bulk have been proposed
in [3] and [4].
Since the gate potential of the bootstrapped switch in the on-state is equal to
the sum of the input and the supply voltages, special attention must be payed to
18
Analog Multiplexers and Switches
the devices connected to that node so that circuit reliability is not compromised.
The constant G-S voltage achieved by the bootstrapping technique means that
the on-resistance is almost independent of the ratio between the supply and the
input voltages, allowing the bootstrapped switch to be used for signal voltages
that go beyond the supply rails. This makes the bootstrapped switch the perfect
(if not the only) candidate for implementation of the video multiplexer, thus it
has been selected for realization.
2.3
The implemented analog switch
Several circuits, proposed in [2], [3] and [4], have been considered for the implementation of the bootstrapped switch. The circuits described in [3], despite promissing
good performance, were excluded from consideration for implementation due to
the fact that they are protected by patents.
The bootstrapped circuit suggested by Waltari et al. in [4] compensates for
the harmful body-effect and can be implemented in a standard, single-well CMOS
technology. This is made possible by the use of a PMOS device with a bootstrapped bulk as the main switch. Special arrangement of the auxiliary switches
is necessary in that case in order to accommodate the large negative voltages that
occur at the bootstrapped nodes. Due to the supposed high performance this
circuit has been selected for realization and further assessment.
Another circuit implementing the bootstrapping technique which utilizes a
NMOS as the pass-transistor is suggested by Lillebrekke et al. in [2]. This circuit
is significantly simpler than the one from [4] and despite the supposedly poorer
performance due to the body effect has also been considered for implementation.
The two selected circuits have been implemented in the target CMOS process
and their behavior has be simulated. It was discovered that for comparable sizing, and despite the improved variation of the on-resistance, the circuit utilizing a
PMOS switch showed much worse performance in terms linearity and bandwidth.
This can be explained by the inherently higher on-resistance of the PMOS transistor which limits the bandwidth and linearity of the switch as whole. It should
be noted that in the case of the multiplexer the capacitance seen at the output
node is significant (at the order of 2 pF), therefore, high on-resistance cannot be
tolerated. Also, the output capacitance has a largely non-linear behavior caused
by the junction capacitance introduced by the switches in the off-state.
Due to the above reasons the bootstrapped switch in [2] has been selected for
the actual implementation and for detailed analysis. The complete circuit of the
switch, as originally presented in [2], is shown in figure 2.7.
2.3.1
Bootstrapped switch—principle of operation
The topological diagram of the circuit from figure 2.7 is shown in figure 2.8. The
operation is based on two non-overlapping clock/control signals, shown in figure
2.9. When clk1 is high and clk2 is low the gate of the pass transistor is grounded
through S5 and the switch is in the off-state, also S3 and S4 are closed and the
2.3 The implemented analog switch
19
bootstrap capacitor Cboot is charged to the supply voltage difference. In the onstate the bootstrap capacitor is connected through S1 and S2 to the source and
gate terminals of the pass transistor turning it on. The non-overlapping nature of
the clocks prevents the bootstrap capacitor from discharging during the transition
between the on and off states. In the on-state the potential between the gate
and the source is approximately constant and equal to the capacitor pre-charge
voltage.
The circuit in figure 2.7 is a direct implementation of the discussed topology.
Transistors N3 and P4 implement S3 and S4 respectively, while transistors N1 and
P2 – S1 and S2. When the current through the pass transistor changes direction
the role of its terminals swaps, this requires the use of N8 which compensates for
this effect and allows node A to more precisely track the potential of the terminal
acting as the source. For high input voltage levels the potential at node B may
become higher than Vdd which requires the transistors connected to that node to
be of PMOS type so that they can conduct reliably. It is not possible to turn on
transistor P2 by simply connecting its gate to ground as voltages exceeding the
gate oxide breakdown limit may appear between its gate (ground) and source (node
B). Therefore, in order to to turn on P2 the voltage of the bootstrap capacitor is
used, this is achieved by transistors N6 and NS6. The dummy transistor PD is
used to compensate for the charge injection due to P7 at node E. Transistors N5
and NS5 implement S5. When the voltage at the gate of the main switch reaches
approximately the supply voltage, transistor NS5 cuts off and limits the voltage
at node Q to a safe level.
Vdd
P4
ChrgLO
ChrgHI
P7
N3
Cbootstrap
A
B
ChrgLO
NS6
P2
Vdd
N1
ND
G
Vin
swOFF
ChrgLO
S
SW
D
NS5
N5
Vout
N8
N6
Figure 2.7: Detailed schematic of the bootstrapped switch presented in [2]
20
Analog Multiplexers and Switches
Vss
CLK2
Vdd
S3
S4
CLK2
Cboot
A
CLK1
B
S1
S2
CLK1
CLK2
Vss
S5
Vout
Vin
SW
Figure 2.8: Topological diagram of the bootstrapped switch
clk2
clk1
Figure 2.9: Non-overlapping control signals used with the bootstrapped switch
Chapter 3
DC restore block
As discussed before, in most analog video systems the external input signals are
AC coupled in order to provide protection against dangerous DC currents and
to allow each device to set its own common mode level. By specification the
external connections of the designed video AFE are AC coupled as well and the
first block in the signal path, the input multiplexer, must provide the means to
set the DC level. In this chapter we discuss the different implementations of the
DC restoration block, their advantages and disadvantages and the reasons why a
particular implementation is suitable for the video AFE or not.
3.1
The need for DC restoration
A typical AC coupling of a video signal into a processing device is shown in figure
3.1, where Rin represents the input impedance of the device. For this arrangement,
the coupling capacitor stores the average value of the input signal, as well as the
difference in the DC level of the signal source and the device input bias level. For
systems that process zero-mean signals, such as audio, this is not a problem as the
bias level is well defined. However, the video signal average level is strongly dependent on the image content, this causes the DC level after the coupling capacitor to
vary. Figure 3.1 shows this behavior for two video signal cases, one representing a
picture with high brightness and the other—with low, shown also, is a zero-mean
sinewave signal for which the DC level does not change. The variation in DC level
would cause the brightness of the image to change in response to changes in the
average brightness. To prevent this effect a DC restoration, or clamp, circuit is
needed to fix the level of the video signal to a known reference level.
The simplest form of a DC clamp circuit is shown in figure 3.2. The switch
S1 can be activated during the hsync pulse, thus, “clamping” the tip of the hsync
pulse to ground level, this is called sync tip clamping. It is, also, possible to
activate the switch during the blanking level of the back porch, fixing the black
level to 0V, this is called black level clamping. Since the sync pulse voltage is
usually not well defined and, also, may not be very stable from line to line, the
21
22
DC restore block
0V
0V
Vin
Video precessing device
Ccouple
Rin
Ileakage
Figure 3.1: Effects on the signal levels due to AC coupling.
Synch tip clamp
0V
Black Level clamp
0V
0V
Vin
Video precessing device
Ccouple
Clamp
S1
Figure 3.2: AC coupling with DC restoration.
3.2 Voltage-mode DC clamp
23
black level clamping provides much better DC stability than the sync tip clamping.
3.2
Voltage-mode DC clamp
The switch in figure 3.2 does not necessarily have to be connected to ground—it
can be connected to any other DC reference (figure 3.3) so that the clamp level can
be chosen arbitrary. This allows a propper bias level to be defined for the following
circuitry by simply changing the reference voltage. This arrangement for which
the DC level is directly forced to a known reference voltage is called voltage-mode
clamping. In fact, the specification for the DC restoration for this thesis requires
that the DC level should be possible to be set anywhere in the range from 100 mV
to 500 mV—a voltage that should only be reproduced, not generated, by the clamp
circuitry.
Vin
Video precessing device
Ccouple
Clamp
S1
Vref
+
Figure 3.3: Voltage-mode DC restoration.
The purpose of the operational amplifier in figure 3.3. is to buffer the reference
voltage Vref and provide a low-impedance source for charging and discharging
of the coupling capacitor in a reasonable time. However, the precision and the
speed of the operational amplifier limit the performance of this circuit. Due to the
poor properties of the transistors in sub-micron CMOS technologies, the design
of amplifiers with reasonable gain and offset is a challenging task. Due to this
reason and the preference for a more “digital” design the voltage-mode clamp is
not considered to be an appropriate candidate for implementation in the designed
multiplexer.
24
3.3
DC restore block
Current-mode DC clamp with current sources
The buffer of the voltage-mode clamp can be substituted by two much simpler
current sources, as shown in figure 3.4 When the DC level needs to be increased the
current source connected to the input node with its positive terminal is activated
and the right plate of the input capacitor is charged to the positive supply voltage.
When the DC level needs to be decreased the other current source is activated and
the capacitor is charged in the reverse direction. This arrangement is, also, termed
charge pump due to the apparent pumping of charge on the capacitor plates.
Vin
Video precessing device
Ccouple
Clamp
S1
ctl
Figure 3.4: Current-mode DC restoration.
In a digitizer application, it makes sense to utilize the main ADC in the feedback loop for sensing the DC level and controlling the DC clamp level. The
current-mode clamp, also called charge pump, is readily suited for control directly
from the digital domain, that is, the current sources need be just on or off. A
conceptual representation of the current-mode clamp with the main video ADC in
the loop is illustrated in figure 3.5. Note that this topology highly resembles that
of the voltage-mode clamp, but instead of the analog reference voltage a reference
digital code is used, and that the analog buffer is replaced by a digital comparator
which generates the “UP-DOWN” control signal.
It should be emphasized that the clamp circuit in figure 3.5 does not operate
in continuous time. Certainly, the ADC samples the continuous-time input signal
and produces output only at certain instants of time. Furthermore, the charge
that is stored on the capacitor plates is proportional to the time the charge pumps
are activated, thus the loop-gain is dependent on the timing.
Due to its “digital” nature the current-mode clamp is far better suited for
implementation in CMOS technology. It should be noted that a digital comparator
consumes far less power and die area and is, also, much simpler to design and
layout. Due to the above said, the current-mode clamp has been selected for
further consideration for implementation in the video AFE.
3.4 Current-mode DC clamp without current sources
25
Vin
Video precessing device
Ccouple
up
Digital
Comparator
Video
ADC
Reference word
down
Figure 3.5: Closed-loop operation of the current-mode clamp utilizing the main
video ADC.
3.4
Current-mode DC clamp without current
sources
The current sources of the current-mode clamp described above can be implemented with two MOS transistors as shown in figure 3.6 where transistor Ns acts
as a current source and transistor Nsw —as switch for turning the clamp on or off.
up/down
up/down
Iclamp
Iclamp
Nsw
Vbias
Ns
Figure 3.6: Realization of the controlable current source.
In order for transistor Ns to be in saturation and actually act as a current
source the condition VGS < VDS + VT H must be met. In the extreme case, the
drain-source voltage (VDS ) drops to 100 mV (the minimum clamp voltage) which
means that the maximum overdrive voltage (VGS − VT H ) can be at most 100 mV.
Simulations, carried out with these constraints, showed that in order to make the
clamp current sufficiently large the width of that transistor must be made in the
26
DC restore block
order of 150 µm. Furthermore, the output resistance of the transistors in the target
CMOS technology is very low, this directly translates to a low output impedance
of the current source making the clamp current strongly dependent on the input
voltage.
It should be noted that due to the short channel effects the output resistance
(seen at the drain) of short-channel devices does not show significant dependence
on the operating mode of the transistor, making the transition between the linear
and saturated region smooth and almost indistinguishable. It makes sense, then,
for the clamp circuit to remove the current source (transistor Ns ) and leave only
the switch (transistor Nsw ), significantly reducing the size and complexity of the
circuit.
Let us, now, follow one possible operation of this “stripped down” version of
the clamp circuit in more detail. First, the voltage of the part of the video signal
that is to be “clamped” is sampled and converted by the ADC, note that the
ADC convertion is running independently of the clamp block and the sample of
interest is simply taken from the ADC output stream. The sample value (code)
is then compared to the reference (target) value and the U P − DOW N signal is
generated, i.e. it is decided if the DC level should be increased or decreased. The
clamp is then activated for a predetermined amount of time (maximum of 6 pixels,
according to the specification) and a specific amount of charge is placed on the
input capacitor plates, thus shifting the DC level at the input.
Here it must be emphasized that since the current through the clamp transistors
is strongly dependent on the signal level to be clamped, the amount of charge put
on the input capacitor per cycle is, also, different for different DC levels. This
makes the clamp settling response non-linear, however, this is not of significant
importance as only the final, settled value, and the settling time is of interest for
the operation of the video digitizer. It is also important to show that the clamp
behavior is stable, that is, it does not oscillate from cycle-to-cycle. This will be
shown in section 5.3.
Due to its “digital” nature and good results from the initial simulations the
topology described above has been selected for the actual implementation in the
video multiplexer.
3.4.1
The implemented DC clamp
So far, the topology discussed for the clamp block has been somewhat simplified
to ease its presentation. In practice, however, the clamp current cannot be simply
switched on and off because this would make the precision with which the DC
level is set too low. Let us consider the change in voltage of the input capacitor
(and the DC level) for one activation of the clamp, it can be written as:
∆Vin =
∆t · Iclamp
Cin
(3.1)
where Iclamp is the clamp current, Cin is the input capacitance and ∆t is the time
the clamp is active, i.e. enabled. The clamp time is more or less fixed, as the
clamp can be active for at most 6 pixels and the smallest practical time is one
3.4 Current-mode DC clamp without current sources
27
system clock period. This means that in order to make the clamp precise the
clamp current has to be very small, which would make the transient behavior very
slow as well. To circumvent this, the clamp current is made controlable, so that
when the error (difference between the target DC level and the actual DC level)
is small the current can be set to be small as well, allowing for the DC level to
be changed in small increments. For large errors, the clamp current can be made
bigger, so as to speed-up the transition.
The adjustment of the clamp current is made possible by connecting several
clamp current transistors in parallel and enabling only some of them (note the
resemblance to a current steering DAC). The need for more signals to control the
operation of the clamp means that the digital comparator of figure 3.6 must now
be changed to a subtractor which calculates the error code and applies it to the
clamp as a control signal.
It is, also, possible to implement a much more complex control strategy of the
DC clamp. For example, during the initial transient, when a particular multiplexer
input is selected, the DC level may be at a completely wrong voltage, in that case
the clamp may be activeted for much longer time—even during the active video
portion of the signal. This will allow shorter settling time than possible if the clamp
is activated only during the back porch. Of course, a more complicated control
block than the simple subtractor will be required to implement such behavior. The
clamp control strategy is, however, out of the scope of this work.
Chapter 4
Analog Multiplexer performance metrics
In this chapter, we will introduce the main performance metrics that were used to
guide the design process of the analog multiplexer and the accompanying clamp
circuitry. We will first relate each metric to the particular non-ideal behavior that
limits the corresponding performance. Then, we will show how the video signal
and the digitizer as a whole are affected, giving examples where appropriate.
4.1
Bandwidth
Probably, one of the most common and popular specification parameters for a
video or graphics system today is its resolution. The resolution is the ability to
distinguish between small details in the reproduced picture. The details of an
image can be present both in the light intensity (brightness), or in the color of the
objects. High detail in an image corresponds to rapid changes in the video signal,
which means that in order to represent high resolution the analog video signals
must have wide bandwidth. Figure 4.1a shows a commonly used test pattern for
video systems, while in figure 4.1b the same pattern is shown but this time the
bandwidth of the underlying signal has been limited. Notice that the vertical
boundaries between the different color patches have become blurred and that the
fine vertical black-and-white stripes have practically turned into a grey rectangle.
Any real analog signal is subject to bandwidth limitation, including the analog
video signal when being processed and transmitted. As discussed in chapter 2,
the finite on-resistance of the switches in the multiplexer together with the input
capacitance of the next module in the digitizer channel form a low-pass filter which
limits the bandwidth of the video signal being processed.
In order to accommodate all available video and graphics formats available
today the 3 dB bandwidth requirement for the video multiplexer is defined by
specification to be 500 MHz. In fact, this is much larger than what is required
for the currently available video formats, but is chosen as such in order for future
29
30
Analog Multiplexer - performance metrics
(a) Normal
(b) Limited bandwidth
Figure 4.1: Effect of bandwidth limitation of the video signal.
formats to be supported as well.
4.2
Linearity
As was discussed in section 1.5, the color and brightness information is contained
in the amplitude of the analog video signal during the active video portion. This
is why it is important that when video is processed the relative amplitude of the
signal is preserved, excluding any gain. Linearity is defined as the property of a
system to respond to the sum of any two inputs with an output which is the sum
of the output responses corresponding to each of the two inputs taken separately.
Any non-linear system introduces non-linear distortion to the signals it processes.
If a video signal is non-linearly distorted the color and brightness information
is lost and the picture will not be displayed properly. The actual effect of nonlinearity on the image depends on the signaling method that is utilized. Suppose
that in a RGB system (for example PC graphics) the color yellow, produced by
the colors green and blue, is to be displayed, Assume, also, that the green and blue
components are with equal magnitudes, corresponding do mid brightness level. If,
now, the brightness of the image is doubled (maximum brightness), but the blue
channel introduces non-linearity and the intensity of the blue color is increased
only 1.5 times, then the green color will dominate and the final image will look
greenish. This effect corresponds to color space deformation. Figure 4.2b shows
the same test pattern as before but with non-linear distortion applied separately
to each of the color channels—red, green and blue. Notice how the color have
changed and that the overall picture brightness have increased.
As was discussed in section 2, the switches in the video multiplexer are subject
to non-linear behavior, hence the non-linear distortion introduced by the multiplexer has been the most important performance metric influencing the design decisions. The actual performance measure used was the spurious-free dynamic range
(SFDR) measured in dBc. Due to the complex non-linear behavior of the switches,
4.3 Inter-channel isolation
(a) Normal
31
(b) Non-linear distortion
Figure 4.2: Effect of non-linear distortion of the video signal.
the SFDR was specified for several input signal amplitudes and frequencies—1 Vp-p
at 20 MHz, 0.8 Vp-p at 40 MHz and 0.2 Vp-p at 1 MHz, with corresponding linearity
of at least 60 dBc, 40 dBc and 80 dBc.
4.3
Inter-channel isolation
It is possible that the signal at a multiplexer input, that is not currently selected,
to leak through the open switches and mix with the signal from the active input.
Depending on the video formats of the two signals this interference may appear
in the final image as noise or as a background ghost image. If the two signals are
with completely different formats, for example TV and computer graphics, they
are not correlated and the interference appears as noise in the form of “crawling”
diagonal lines. However, if the signals are with the same format, for example from
two TV tuners, then they have the same horizontal and vertical refresh rates and
the image from the interfering input may be visible on the screen.
The inter-channel isolation has been specified to be at least 70 dBc for all
frequencies in the range 0-500 MHz.
4.4
Clamp circuit performance metrics
The primary purpose of the clamp circuit is to define the DC level of the video
signal and keep it stable throughout the frame, it is also required to initially bring
the DC level to the target voltage in a timely manner. If the clamp circuit is not
stable, that is the DC voltage oscillates between the lines, then horizontal stripes
with varying brightness will be visible on the screen. This is a highly undesirable
effect since the human eye is very sensitive to different brightness levels. The result
from unstable behavior of the clamp circuit is shown in figure 4.3b. Note that,
despite of the small random variation of at most ±5% applied to the DC level the
variation in brightness is quite visible.
32
Analog Multiplexer - performance metrics
The performance measures that guided the design of the clamp circuit were
stability and settling time. The settling time was specified to be at most 1 frame.
(a) Normal, stable DC level
(b) Unstable DC level
Figure 4.3: Effect of unstable DC clamp. The brightness is varied by 5%.
4.5
Leakage and lower cut-off frequency
As discussed earlier, the video signal is AC coupled to the input of the multiplexer
through an external capacitor which “holds” the DC level during the active video
portion. If a small current leaks through the internal circuits of the digitizer
channel of the video AFE, the DC level of the signal will change throughout the
line. On the screen, this will be visible as a changing brightness of the image from
left to right as shown in figure 4.4b. This effect can also be viewed as a too high
(a) No leakage
(b) Excessive leakage
Figure 4.4: Effect of leakage current through the input capacitor.
lower cut-off frequency, this is indeed possible as the AC coupling acts as a high-
4.5 Leakage and lower cut-off frequency
33
pass filter. In the early video systems the problem with leakage through the input
coupling capacitor (also called “line droop” or “line tilt”) was quite severe, but
in modern systems it is easily corrected in the digital domain. Nevertheless, such
correction reduces the available range of the ADC and leakage must be limited as
much as possible in the analog domain.
Note that the brightness at the rightmost edge of the image in figure 4.4b. is
only 5% lower than that at the leftmost, still it is clearly visible.
The amount of change in DC level per line is not explicitly specified in the
design specifications, but a value no bigger than 1 LSB of the main video ADC
was targeted in the design of the multiplexer and clamp circuits.
Chapter 5
Design Details
5.1
Introduction
So far, we have only discussed the different blocks of the input multiplexer in terms
of their expected performance and different implementation strategies, we have
also selected a particular schematic to be realized for each block. In this chapter,
we will describe the design details for each circuit, give detailed transistor sizing
strategies and the rationale and trade-offs behind the design decisions.
Due to the relative simplicity of the interaction between the blocks comprising
the multiplexer, it was possible to carry-out the design in the meet-in-the-middle
fashion, without building behavioral models for the different blocks. Note that the
behavior of a switch, even with parasitics, is not particularly interesting.
First, the bootstrapped switch topology, presented by Lillebrekke et al. in
[2], was implemented and the circuit behavior studied in detail in order to verify
that it is suitable for the purposes of an analog switch in the multiplexer. Several
modifications of the original circuit were proposed and successfully implemented.
A behavioral model was, then, built for the clamp block and its operation together
with the switch was studied and simulated in order to identify potential problems.
The clamp circuits were, then, implemented at transistor level and resimulated.
Finally, the whole multiplexer was connected together and thoroughly simulated
in order to identify shortcomings and potentially fix them. During this phase the
analog switches were resized in order for all specifications to be met.
5.2
Bootstrapped switch
The selected in section 2.3 analog switch schematic was implemented in the target
CMOS technology and the circuit operation was assessed in terms of performance
and robustness. The detailed schematic of the switch is shown in figure 5.1, this is
the original schematic as presented by Lillebrekke et al. The Spectre™ simulator
analog language VerilogA was used to describe the behavior of the non-overlapping
clock generator and the input signal generator. This allowed to quickly switch
35
36
Design Details
between different simulation set-ups.
Vdd
P4
ChrgLO
ChrgHI
P7
N3
Cbootstrap
A
B
ChrgLO
NS6
P2
Vdd
N1
N6
ND
swOFF
ChrgLO
G
Vin
S
SW
D
NS5
N5
Vout
N8
Figure 5.1: Detailed schematic of the bootstrapped switch presented in [2]
The primary objective of these initial simulations was to explore the design
space and the main trade-offs for the design of the bootstrapped switch. As was
expected, the bandwidth and linearity of the switch are highly dependent on the
size of the pass transistor (denoted by SW in figure 5.1) and both increase by
increasing the transistor width. Also, both linearity and bandwidth increase when
a transistor with a lower threshold voltage and/or a thinner gate oxide is used as
the main switch. The main loading effect for the switch in figure 5.1 is the output
load capacitance, as such, its size also directly affects the performance.
5.2.1
Special design considerations
Originally, the selected bootstrapped switch circuit was designed for switched
capacitor (SC) applications which have somewhat different requirements for the
switch performance. This imposed different requirements on the design and required some modifications of the original switch circuit.
5.2 Bootstrapped switch
37
In order to achieve high clock rates in a switched capacitor circuit the switches
are required to change state very fast and with minimum delay, in the multiplexer
environment this is not the case as the switching time is not of particular interest.
Actually, the time needed for the circuits following the multiplexer to resynchronize
to a different video source is several orders of magnitude bigger than the time
needed for any electronic switch to change state. Hence, the switching time is not
taken into consideration when designing the bootstrapped switch.
Also, in order not to introduce significant noise and offset the switches for
switched capacitor applications are required to keep the clock feedthrough and
charge injection to a minimum. For the video multiplexer it is not a problem if a
glitch is introduced at the output when inputs are switched as at that instant the
video signal is not even processed further. Hence, the dummy transistor ND from
the original circuit shown in figure 5.1 is removed and is not implemented in the
final design.
Another big difference in the requirements for the switches designed for switched
capacitor applications and those for the video multiplexer is the time for which
the switch is supposed to continuously operate in the closed (on) state. For static
switches like the transmission gate, for example, this is not a problem, but for the
bootstrapped switch, which has a dynamic nature, the charge on the bootstrap
capacitor has to be periodically refreshed to compensate for leakages. In SC circuits, where switches are toggled with a few megahertz, this is done during the
off-state (open). However, in the case of the video multiplexer, the witches must
be closed continuously and cannot be turned off for charging, so there must be a
mechanism provided for charging without opening the switch. This is achieved by
adding the transistors N8, NS8 and P7 as shown in figure 5.3, this also means that
now separate control signals are used for turning the switch off and for charging
of the bootstrap capacitor. Since, in order to be recharged the bootstrap capacitor has to be disconnected from the main switch transistor terminals, the output
signal will be significantly distorted during that time, therefore, the recharge cycle
should be executed only during the blanking interval. However, due to the capacitance present between the source and gate terminals of the main pass transistor
the switch will continue to operate in the closed state.
During the initial simulations of the switch circuit it was discovered that a
situation potentially damaging the switch circuit may occur. Consider the circuit
as shown in figure 5.2, if the input voltage drops to a level such that the voltage
at node B becomes lower than the supply voltage with more than the threshold
voltage of P4, it will turn on and cause current to flow through the bootstrap
capacitor, as shown in figure 5.2. Note that, the gate voltage of P4 is equal to
its drain voltage (node B), hence it acts as a resistor for drain voltages higher
than Vt . The resulting current will charge the bootstrap capacitor to the voltage
difference of the input and supply voltages, minus one threshold voltage. It is
actually possible for negative voltages to appear at the input node which means
that the bootstrap capacitor will be charged to a voltage bigger than the supply.
For example, if the input voltage drops to 450 mV (the ESD protection operates
at approximately 600 mV) and if the supply voltage is at its maximum of 1.2 V
then the bootstrap capacitor will be charged to 1.2 V+450 mV-250 mV=1.4 V
38
Design Details
(assuming that the threshold voltage is 250 mV). This voltage when applied to the
gate-source terminals of the main pass transistor will significantly reduce the life
of the circuit. Note, also that in some process corners the threshold voltage may
be lower than 250 mV, further aggravating the situation.
Vdd
P4
ChrgLO
ChrgHI
P7
N3
Cbootstrap
A
B
ChrgLO
NS6
Vdd
N1
N6
P2
NS5
Vin
G
S
N5
SW
D
Vout
N8
swOFF
Figure 5.2: Harmful current through the bootstrap capacitor due to low negative
input voltages.
The problem is solved by the addition of the transistor PS4 as shown in figure
5.3. During the on phase the control signal, and thus the gate of P4s, is at a high
voltage, approximately equal to the positive supply, this means that the transistor
PS4 will stay off for any voltage at node B lower than the supply. For voltages at
node B higher than the supply, PS4 will turn on, but this is not a problem since
transistor P4 will then be off.
The switch schematic shown in figure 5.3 is the actual schematic implemented
in the input multiplexer.
5.2 Bootstrapped switch
39
Vdd
ChrgHI
P4
ChrgLO
N3
P7
PS4
Cbootstrap
A
ChrgLO
Vdd
ChrgHI
B
P7
ChrgLO
NS8
N8
NS6
Vdd
N1
N6
P2
q
G
S
Vin
swOFF
NS5
N5
SW
D
Vout
N8
Figure 5.3: The full schematic of the bootstrapped switch as implemented in the
final version of the design.
5.2.2
Switch linearity and bandwidth
In section 2.2 we discussed that the main source of non-linearity in a MOS transistorbased switch is the variation of the gate-source voltage of the switch pass transistor. While the bootstrap technique largely eliminates this variation there are a
few other sources of non-linearity that limit the performance of the switch.
So far, we have neglected a significant source of non-linearity in the analog
switches, this is the non-linear junction capacitance introduced by the reverse
biased source-bulk and drain-bulk PN junctions. The capacitance of a reverse
biased PN junction is given by
CJ (VJ ) =
CJ0
(1 −
VJ
mj
VDif f )
(5.1)
where CJ0 is the zero-voltage capacitance, VJ is the junction voltage, VDif f
is the diffusion voltage and m ≈ 1/3 . . . 1/2 is the capacitance coefficient. Therefore, the voltage over a non-linear capacitor charged through a resistor depends
non-linearly on the input driving voltage. Also, the non-linear behavior is more
clearly pronounced for lower capacitor voltages and bigger resistances.
The non-linear junction capacitances that occur in the switch circuit and affect
40
Design Details
its performance are shown in figure 5.4 with black heavy lines and denoted by Cnli .
The greatest effect on linearity is caused by Cnl1 and Cnl2 at the drain and the
source of the main pass transistor SW. They appear directly in the signal path
and are charged to the instantaneous voltage of the input video signal through the
equivalent resistance of the pass transistor channel and the external termination
resistance. Also the magnitude of these two capacitances is the greatest since the
transistor SW is far bigger than the rest.
Vdd
ChrgHI
P4
ChrgLO
N3
P7
PS4
Cbootstrap
A
ChrgLO
Vdd
ChrgHI
B
Cnl4
Cnl3
NS8
P7
ChrgLO
N8
NS6
Vdd
N1
N6
P2
q
G
Vin
S
Cnl2
NS5
SW
N5
Cnl5
D
Cnl1
Vout
N8
swOFF
Figure 5.4: Non-linear junction capacitances affecting the linearity of the bootstrapped switch.
The capacitances Cnl3 , Cnl4 and Cnl5 , caused by the transistors connected to
nodes A, B and G, respectively, also contribute to the non-linear behavior. Notice
that they appear in the signal path from the input node to the gate node of the
main pass transistor. This means that the AC component of the input signal is
distorted before it reaches the gate of the pass transistor creating an AC voltage
difference between the source and gate terminals of transistor SW, which results
in variation of the on resistance. This contribution is, however, relatively small.
The discussion above suggests that a trade-off can be made between the size
of the main switch, the threshold voltage and the load capacitance. Also, in order
to keep parasitics to a minimum the auxiliary transistors must be kept physically
small.
Note that, when the circuit is switched from the off state to the on state the
5.2 Bootstrapped switch
41
parasitic capacitance between the source and the gate of SW must be charged
by the bootstrap capacitor. Thus, the bootstrap charge is redistributed and the
available overdrive voltage for the main switch is lowered. This suggests a trade-off
between the size of the bootstrap capacitor and the main switch size and threshold
voltage can be made.
The body effect is inherent to all integrated NMOS devices in a single-well
CMOS technology, as the one used for this design. The body effect causes the
threshold voltage to increase with the increase of the source-bulk voltage. This
effect cannot be fully eliminated for the selected circuit topology, however, it can
be minimized by selecting a transistor with a higher threshold voltage, i.e. the
relative variation can be reduced. Despite of that, since the transistors with higher
threshold voltage are more resistive for the same driving voltage the overall linearity is not improved. This is because, as shown above, the non-linear loading
capacitance now has a bigger effect on the total non-linearity.
5.2.3
Bootstrap charge retention
The operation of the bootstrapped switch is based on the ability of the bootstrap
capacitor to hold sufficient charge between recharging events. In order not to affect
the video signal the only possibility to recharge the bootstrap capacitor is during
the blanking periods, this means that enough charge must be stored for the period
of one line, i.e. the hsync period. This proved to be a major limitation of the
performance of the circuit since, as expected the transistors of the target CMOS
technology were found to present substantial leakage currents both through the
gate and between the D-S terminals when operating in the cut-off region.
Figure 5.5 shows the switch circuit when in the on-state, for clarity the transistors that are ON are shown with heavy black lines, while those that are off are
shown with light grey lines. The leakage current through the bootstrap capacitor
has several components, denoted with In and shown with different line colors in
figure 5.5. The leakage current components notation is chosen such that only one
device determines the magnitude of each particular component.The currents I3 ,
I4 , are determined by the gate leakage of transistor P2, and N1 and N8 combined, respectively, while I2 , and I5 are due to the drain-source leakage in the
cut-off region of transistors N5 and P4, respectively. The leakage component I1 is
determined by the gate leakage of the main switch transistor SW.
Due to the availability of several different transistor types in the target CMOS
technology there are many ways to reduce the leakage currents, however, this introduces design trade-offs. In order to reduce the D-S leakage a transistor with a
higher threshold voltage can be used, also, short wide transistors have higher leakage than transistors with narrower and longer channels. Loosely, the “stronger”
transistors have more drain-source leakage, with the threshold voltage having the
greatest effect. The gate leakage can be reduced by using low-power, thicker oxide
transistor types, but they are also “weaker”. Transistors with greater gate area
also have bigger gate leakage, so increasing either the length or the width also
increases the gate leakage.
The above means that the ability of the switch to operate for longer periods
42
Design Details
Vdd
P4
ChrgLO
ChrgHI
P7
N3
I5
Cbootstrap
A
B
I2
ChrgLO
I3
N8
N6
N1
I4
Vdd
P2
G
I1
Vin
swOFF
S
NS5
N5
SW
D
Vout
NS6
Figure 5.5: Currents discharging the bootstrap capacitor due to device leakages.
Transistors shown in black are ON.
without recharging, i.e. to retain the bootstrap capacitor charge, can be traded for
several other parameters. The size of the pass transistor SW has the major effect
on the circuit performance, thus, it has to be substantially larger than the rest of
the transistors included in the switch circuit. Due to that, this transistor also has
the biggest contribution to the leakage current. Thus, the trade-off is bandwidth
and linearity for charge retention. In order to minimize the current I2 transistor
N5 must be of high Vt type, however, this makes it weak and limits its ability to
drain the current injected through the gate of transistor SW and keep it cut-off
when the switch is in the off-state, i.e. when N5 is on. This means that a trade-off
between charge retention and isolation in the off-state can be made. Also, to limit
the leakage through the gates of P2, N1 and N8 their area have to be kept small
and they have to be of low-power type, which makes them weak as well. Luckily,
since they do not present D-S leakage problems they can be of low Vt type in order
to compensate for the loss in driving capabilities. The reduced driving strength of
these three transistors leads to a decrease in linearity as the gate-source voltage
can not be kept constant. The leakages through N3 and P4 can be reduced by
5.2 Bootstrapped switch
43
making these transistors of high Vt type, but the reduced driving strength means
that longer time for charging of the bootstrap capacitor will be needed.
5.2.4
OFF-state resistance and isolation
In order to provide sufficient attenuation for the signals at the non-active inputs of
the multiplexer the switches must have a high off state resistance. As mentioned
above, in order to turn the bootstrapped switch off its gate is connected to ground.
However, since the DC level at the inputs that are OFF is not controlled in any way,
it is possible that negative voltages appear at the input of the switches that are in
the off-state, effectively turning the pass transistor on and reaching the output of
the multiplexer. Furthermore high frequency signals may be capacitively coupled
from the input of a switch to its output and reach the multiplexer output.
SwOut
Vin
Vout
SwIn
SwMid
(a) Open, non-conducting state
SwOut
Vin
Vout
SwIn
SwMid
(b) Closed, conducting state
Figure 5.6: T-switch arrangement used for the multiplexer switches implementation.
In order to circumvent these problems, two switches are connected in series,
while the middle common node is grounded by a third switch when no signal should
be passed. This arrangement, naturally called a T-switch, is shown schematically
in figure 5.6. When the T-switch is in the off, non-conductive state, the two
“horizontal” switches (SwIn and SwOut in figure 5.6) are off, while the third one
is on, hence, any signal that passes through the input switch is grounded and its
amplitude is significantly reduced, such that the output switch can more effectively
stop the signal from reaching the multiplexer output.
It must be noted that, only switches SwIn and SwOut must have high linearity
in the on-state as they conduct the video signal when the T-witch is in the on-state,
44
Design Details
while the middle switch SwMid should only provide low impedance to ground when
turned on. Therefore, the middle switch can be a simple NMOS transistor with
sufficient size.
5.3
DC restoration circuit
In section 3.4.1 we described the basics of the implemented DC restoration method
and circuit, here we will present the design details and discuss the transistor sizing
strategy.
The circuit topology of the charge pumping block of the DC restore circuit is
shown in figure 5.7, it consists of two sections of transistors—a pull-up and a pulldown section. Each section consists of 31 identical (unit) transistors connected
in parallel, the number of active transistors is controlled by a 5-bit digital word.
The direction of the output current is controlled by activating either the pull-up
or the pull-down transistors. The DC restore block can be viewed as a closed-loop
Pull-Up
Vdd
31
P1
Werr
sign
P2
P31
5
Iclamp
control
logic
31
N1
N2
N31
Cin
Pull-Down
Figure 5.7: Charge pump with a 5-bit controllable current implemented with simple transistor switches.
system, as shown in figure 5.8, the input control variable WinDC is a digital word
representing the target DC level and the output variable WoutDC is the value of
the output sample from the video ADC which corresponds to the portion of the
video signal whose level is to be controlled (back porch for example). Since the
behavior of the charge pump is highly non-linear the closed-loop system cannot
be analyzed by means of a transfer function, therefore time domain analysis have
to be utilized. Nevertheless, it is beneficial to linearize the charge pump circuit
around the operating point determined by the video signal voltage at the time of
5.3 DC restoration circuit
45
Charge Pump
WinDC
12
Cin
Werr
5
Vdd
Video In
Video ADC
WoutDC
12
Figure 5.8: The DC restore circuit viewed as a digital control loop, the input
variable is the target DC level and the output is the controlled and measured DC
level.
activation of the clamp.
The schematic of the charge pump together with the input capacitor is shown
in figure 5.7, the pump consists of two groups of 31 unit size transistors, only
transistors from one group are activated per clamp event (the DC restore circuit
is not continuously active). The number of active transistors corresponds to the
difference between the input variable WinDC and the output variable WoutDC ,
that is, to the error variable Werr . At the operating point, we can consider the
transistors of each of the pull-up or pull-down networks as a controlable current
source with the control signal being the value of the digital error variable, as shown
in figure 5.7. The group of transistors that is to be activated depends on the sign
of the error, that is, whether the DC level should be increased (pulled-up) or
decreased (pulled-down). Note that, if we disregard the quantization of the error
variable the two current sources and the input capacitor behave like a discrete-time
integrator. This means that for the quantized error variable the clamp behaves as
an accumulator, summing up the values of the error variable. In the time domain
this behavior can be expressed as:
∆VDC = Werr
GI (VDC ) · ∆t
Cin
(5.2)
where, ∆VDC is the change in the DC voltage level per clamp activation event,
Werr is the integer error (control) variable, GI (VDC ) is the current gain of the
current sources as function of the output DC level, ∆t is the period of time for
which the clamp is active, and Cin is the capacitance of the input capacitor. The
current gain is dependent on the DC level, since the pull-up/down transistors
operate in the linear region and in practice behave like resistors, however, it is
46
Design Details
more convenient to work with their equivalent current gain in the operating point
determined by the DC voltage.
Note that, the error term Werr corresponds to the digitized version of the
difference between the target DC level and the current DC level measured by the
video ADC. We can instead write:
∆VDC = Verr ·
GI (VDC ) · ∆t
G
·C
{z in }
| ADC
(5.3)
loop gain
where, GADC is the gain of the video ADC, and Verr is the voltage difference
between the target and the current DC levels, note that, this is a fictitious voltage
and does not physically exist in the system.
Observe that, if the voltage change ∆VDC is equal to the current error voltage
Verr then the error voltage for the next cycle will be zero, that is the system
would have settled. Also note, that such system behaves as a unit delay from the
reference input to the output and the output response corresponds to the critically
damped closed loop response.
In order for the equality ∆VDC = Verr to be fulfilled the expression to the right
of Verr in equation 5.3 must be equal to one, that is the loop gain must be unity.
We have:
GI (VDC ) · ∆t
=1
(5.4)
GADC · Cin
rearranging, we get for the current gain:
GI (VDC ) =
GADC · Cin
∆t
(5.5)
For the sizing of the charge pump transistors the current gain is what is actually
needed. If we size the transistors such that the highest loop gain is unity in the
worst case then the system response will be underdamped in all other cases. This
is confirmed by inspection of equation 5.3 — if the loop gain is lower than unity
the change in DC level per period is smaller than the absolute value of the error
voltage.
The worst case for the loop gain occurs for the smallest input capacitor value,
which is given by specification to be 10 nF, the highest ADC gain and the longest
possible activation period. As was discussed in 1.4, the resolution of the video ADC
is 12 bits, it has an input range of 1 V and is preceded by a PGA (programable gain
amplifier) with a maximum gain of 4, therefore the maximum gain of the ADC is
1/4 · (212 − 1) = 61µV /LSB. The clamp time ∆t is defined by specification to be
maximum 6 pixels for the highest pixel rate of 300MHz, yielding ∆t = 6/300.106 =
20ns. Substituting the above values in 5.5 we get for the maximum current gain:
max(GI (VDC )) =
61.10−6 · 10−9
= 30µA/LSB
20.10−9
(5.6)
This value is higher than the minimum permitted by specification value of 20 µA/LSB,
thus, the transistors in the charge pump are sized such that the in the worst case
the maximum current per LSB to be 30 µA.
5.3 DC restoration circuit
47
In the above calculations we assumed that the input coupling capacitor is
10 nF, this value is rather low and in practice a capacitor with a higher value is
usually used. In such cases the settling time of the DC restore circuit may become
excessively long, to compensate for that a longer activation time may be used.
This is indeed possible since most video formats have pixel rates much lower than
the 300MHz rate assumed above.
The number of bits specified as the precision of the DC restore block is 5,
hence, the clamp current can be controlled in 215 -1=31 steps. With the above
calculated value for the current per 1 LSB the maximum current when all bits
are active becomes: 31·30 µA = 930 mA. This is less than half of the maximum
permitted current of 2 mA, so in order to fully exploit the design margin the
transistor in the charge pump that is activated for the highest value of the digital
control word is sized such that when all bits are at a high state the output clamp
current is 1.98 mA. This means that the largest output current corresponds to
66 LSB, thus with this small modification the settling time is more than halved
while the resolution is kept the same. The resulting transfer characteristic of the
charge pump is shown in figure 5.9 for all values of the digital control word. This
behavior must be taken into account for the design of the control logic that is
going to implement the DC restore block control strategy. For example, for the
control loop from figure 5.8 the result from the subtractor (Werr ) must not be set
to the maximum value before the actual difference becomes more than 66 LSB,
otherwise unstable behavior may occur.
Iclamp [uA]
1980
900
870
60
30
0
1
2
3
30
31
Digital input value [LSB]
Figure 5.9: Transfer characteristic of the charge pump of the clamp block.
48
5.3.1
Design Details
Control signals and actual implementation
The charge pump of the DC restore block is implemented by unit transistors with
parallel connected drain and source terminals, while their gates serve as enable
inputs. This means that a 31-bit thermometer encoded word is needed to control
the operation of the charge pump, furthermore the direction selection of the clamp
current, that is which transistor network is active, is done by a direction (sign)
bit. Figure 5.7 shows the charge pump-circuit together with the required control
logic and the names of the control signals, as implemented at the final stage of the
design.
The functions of the signals shown in figure 5.7 are as follows: bit is a 5-bit
data bus for controlling the clamp current, the data encoding is unsigned binary;
sign controls the direction of the clamp current, when high the pull-up network
is active, when low—the pull-down; en is an enable signal, when low the clamp is
enabled and the output current corresponds to the value at the bit input, when
low the clamp is disabled and all pull-down transistors are turned ON. This rather
strange use of the en signal shall be explained in more detail in the following
section. It is important to mention here, that the binary-to-thermometer decoder
has not been implemented at transistor level, but only as a behavioral model, the
VerilogA code of the decoder is given in Appendix A, there the function of the en
signal and the discontinuity around the 31-st input bit can be seen in more detail.
5.4
Multiplexer topology and top-level design
So far, in order to simplify discussions, we have examined the different blocks
comprising the designed multiplexer somewhat in isolation. In this section we
present the way the different block are interconnected, how they interact with
each other and how the overall performance is affected.
Recall that, the multiplexer switches are implemented as T-switches for which
the most important requirement for the middle switch is to have sufficient driving
strength. This is actually the same requirement as for the pull-up/down transistor
networks of the charge pump of the DC restore block. Therefore, it was proposed
that these two blocks, the T-switch and the DC restore, be integrated into a single
functional unit, so that the pull-down transistor network of the DC restore circuit
can be used as a grounding (middle) switch of the T-switch structure. This is the
reason why a high level of the enable signal for the clamp block is specified to turn
on the pull-down network. The resulting topology for a single multiplexer switch
is shown in figure 5.10 together with the DC restore circuit. Note that the control
logic circuitry is omitted for clarity.
The overall block diagram of the designed 8-input multiplexer is shown in figure
5.11. This is the simplest architecture of a multiplexer, where each multiplexer
input signal is passed to the output through a single switch. In this case the output
parasitic capacitance of all switches is seen at the output of the multiplexer, this
capacitance is a major source of nonlinearity, as discussed in section 5.2.2. In order
to prevent some of this capacitance from loading the currently conducting switch it
is possible to arrange the multiplexer switches in a pyramidal structure. However,
5.4 Multiplexer topology and top-level design
Vdd
SwIn
49
SwOut
Vin
Vout
RESD
ChrgHI ChrgLO swOFF
ChrgHI ChrgLO swOFF
bit
5
en
Figure 5.10: Interconnection of the blocks in a single multiplexer channel as implemented in the final design
for the designed multiplexer such arrangement was not necessary and the required
linearity and bandwidth could be achieved with the simple topology of figure 5.11.
Furthermore, arranging the multiplexer this way makes the physical layout to be
very regular and compact. Also, note that, since for the simple structure of figure
5.11 each switch is a standalone structure and independent of the others (it has
the DC resore and all required control circuitry “built-in”), the multiplexer can
easily be modified by adding or removing input channels.
Since the input of switch SwIn for all multiplexer channels is connected directly
to the integrated circuit bonding pad it must be protected against ESD (electrostatic discharge) by a secondary ESD protection circuit (the primary protection is
in the input pad itself). The secondary ESD protection consists of two clamping
diodes and a series resistor connected between the input pad and the circuit node
to be protected, as shown in figure 5.10. Since the protection resistance, which
must be at least 50Ω and nominally—250Ω, combined with the multiplexer load
capacitance of 1.5pF would limit the bandwidth to an unacceptably low value,
therefore, the pass transistor of the input switch had to be split into seven parallel
instances. Thus, a separate protection resistance with a sufficiently high value was
used for each unit transistor, while the effective (due to the parallel combination)
value that determines the time constant was kept low enough so as not to limit
the bandwidth.
5.4.1
Design considerations and transistor sizing
Up to this point of the design of the multiplexer it was not possible to size the
transistors such that the deign specifications are met. In this section we will discuss
the most important design considerations and the transistor sizing strategy.
During the top-level simulations it was discovered that the input and output
50
Design Details
Vin1
S1
SwIN
Vin2
S2
S3
Vout
Vin3
SwOUT
Vin8
S8
Figure 5.11: Final architecture of the designed multiplexer.
switches of a T-switch do not necessarily have to provide the same performance in
all aspects as they actually bare different functionality in the multiplexer. Obviously, both switches have to provide good linearity in the on-state, but that does
not necessary have to be achieved the same way for both of them. It turns out
that due to the shunt section of the T-switch the input switch does not have to
provide very high levels of signal attenuation in the off-state. This means that the
main pass transistor of that switch can be implemented by a “leaky” low-threshold
transistor which requires much smaller width (therefore, smaller area) in order to
achieve the required linearity and bandwidth.
The sizing of the pass transistor in the output switch is related to more tradeoffs: Firstly, its area must be kept as small as possible in order to limit the
non-linear capacitance introduced at the output node, on the other side, it cannot
be made too small since then the transistor itself will become too resistive and
non-linear. Furthermore, only transistors with high threshold voltage must be
used due to the high leakage currents of the other two types (low and standard
threshold voltage). The leakage current between the drain and source terminals
of the output switch in the T-switches that are off passes through the T-switch
that is on and through its corresponding external coupling capacitor. The effect
of such leakage currents was discussed in section 4.5, where it was explained why
they should be avoided.
Chapter 6
Test bench and simulation
results
In this chapter we first introduce the test bench that was used throughout the
design of the multiplexer and to extract the relevant performance parameters and
verify the design. After that we present the actual simulation results and the
obtained performance parameters together with some comments on them.
6.1
Test bench design
The video multiplexer falls in the, so called, mixed-signal class of circuits, these
are circuits which have both digital signals (usually clocks and control) as well
as analog signals. This type of circuits are particularly hard to simulate, both
due to their complex behavior and due to the long simulation time required. The
complicated behavior arises from the fact that these circuits usually require some
form of set-up sequence on their digital inputs before the behavior with respect
to the analog signals can be simulated. For example, the bootstrapped switches
of the multiplexer must be pre-charged and put in the on-state before linearity
can be analyzed. Furthermore, the digital signals usually have short rise and fall
times forcing the SPICE-like simulators to use short time steps, hence the long
simulation times.
The simulation of mixed signal circuits is further complicated by the great variety of external signal waveforms and timing scenarios that have to be simulated.
For example, in order to verify that the transistors in the bootstrapped switches
are not stressed beyond their breakdown voltages, it was necessary to operate
the bootstrap circuitry for different video signal voltages and switching activities.
Therefore, additional effort was made when the test bench for the multiplexer was
designed.
The performance metrics discussed in chapter 4 are of widely varying nature
and each of them requires a totally different test bench set-up to simulate. Take,
for example, the simulation of linearity and leakage currents through the input
51
52
Test bench and simulation results
capacitor, linearity simulation requires that an input signal with a sinewave be
present, while leakage simulation requires a quiet circuit so that the small leakage
currents are easily measurable. Furthermore, when optimizing a particular performance metric, it is quite likely that another one is compromised (trade-offs),
hence, it is highly beneficial to be able to quickly re-run simulation setups for
different performance metrics. Due to this reason the primary goal in the design
of the test bench was to be able to simulate all scenarios that are of interest with
just one schematic (netlist) of the test bench.
The principle schematic of the test bench is shown in figure 6.1, where the video
signal generator block and the timing and control block were written in VerilogA.
Since the behavior of these blocks has to be different for the different simulation
setups they were written such that their behavior depends on design parameters.
By setting these parameters the environment (for the multiplexer) behavior can
be changed without modifying the netlist. The VerilogA code for the video signal
generator is listed in Appendix B.
75
75
Cin
Horizontal sync
75
75
Cin
Disturbance
75
75
Cin
Simulated multiplexer
Video Signal
Generator
Vout
Inactive Channels
Input selection
and bootstrap
recharge control
Figure 6.1: Block diagram of the test bench used for the simulations of the multiplexer and clamp circuits
The simulations were entirely driven by an OCEAN script which was executed
in the Cadence environment. The script is separated in sections—each section
performs a particular simulation, extracts the relevant parameters (such as bandwidth) and writes them into a text file. Each section is conditionally executed in
case a variable enabling it is set to true, while the enable variables were set manually at the top of the script, this allows only the selected simulation analysis to be
6.2 Simulated performance parameters and results
53
performed. A key element in the OCEAN script is that all design variables (such
as transistor widths) are set by a single function which is called in each section,
this allows a centralized control over the all-important design variables.
6.2
Simulated performance parameters and results
Here we present the results obtained by simulating the designed multiplexer in its
intended operating environment. The performance parameters are separated into
two groups: the first group consists of performance metrics as given in the design
specification and are, therefore, limited by minimum and/or maximum value; the
second group consists of parameters, that we feel, are important for the operation
and future characterization of the designed schematics.
Table 6.1 lists the parameters given in the design specification together with
the results obtained from the simulations of the design. The last column in table
6.1 gives some short explanation of the simulation set-up. The minimum and maximum values are given for the PVT (process-voltage-temperature) corner where
they occur, while the typical values are given for the typical PVT corner.
6.2.1
Internal voltage levels
Since the operation of the bootstrapped switch is based on the addition of the
input voltage with the voltage of the bootstrap capacitor, voltages bigger than the
supply voltage appear on internal nodes of the switch circuit. The original circuit,
as presented by Lillebrekke in [2], is designed such that the transistors are not
stressed by these high voltages. However, since for the multiplexer application the
switches operate continuously for long periods of time, in the presence of possibly
pulsating video signals (for example vertical black and white stripes), it is possible
that charge injected in the floating nodes compromise the reliability and robustness
of the circuit. Special attention has been payed to this phenomenon and the the
switch circuit was simulated with several input signal patterns in order to discover
potentially problematic nodes. As expected, the input signal that caused the
greatest internal node voltages was a square wave.
The bootstrapped switch was simulated with a square wave input with an
amplitude of 1.4 Vp-p and the maximal power supply voltage of 1.2 V, the results
were then processed by an OCEAN script which extracts the maximal and average
currents that flow through the transistors and the maximal voltages that appear
over each combination of two terminals of the transistors. The absolute values of
the extracted voltages and currents are presented in table 6.2, note that, these are
peak values and that the average are usually much lower.
54
Test bench and simulation results
Item
Number
of Inputs
Bandwidth
Linearity 1
Linearity 2
Linearity 3
Isolation
Clamp
Current
Output Load
Capacitance
Clamping
Voltage
Clamp time
DC set time
ESD
protection
Low Supply
voltages
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
simulated
specified
Min
8
8
500
536
60
65
40
60
80
106
70
—
25
15
—
—
100
100
—
—
—
—
50
—
1
Typ
—
—
—
694
—
81
—
78
—
110
—
—
—
30
—
—
—
—
6
6
1
—
100
200
1.1
Max
—
—
—
3469
—
—
—
—
—
—
—
2
2000
1980
—
1.5
500
500
—
—
—
—
—
—
1.2
simulated
1
1.1
1.2
Unit
—
MHz
dBc
dBc
dBc
dBc
LSB
µA
pF
mV
pixels
frame
Ohm
V
Comment
—
Measured at -3 dB below
DC level.
Measured for
Vin =1 Vp-p at 20 MHz.
Measured for
Vin =0.8 Vp-p at 40 MHz.
Measured for
Vin = 0.2 Vp-p at 1 MHz.
Modified specification.
ADC range: 250mV; 12bit
—
Not originally specified.
PGA input capacitance.
Operation outside this
region may be unstable.
Defined by the selected
external control strategy.
Defined by the selected
external control strategy.
—
Can be lowered if the
number of inputs or the
load capacitance is
lowered.
Table 6.1: Simulated performance parameters for across all process corners.
6.2 Simulated performance parameters and results
55
Terminal
Maximal stress
Comment
Maximal (peak) absolute voltages
Drain–Source
2.1 V
—
Gate–Source
1.31 V
—
Gate–Drain
1.34 V
—
Bulk–Source
1.31 V
Forward bias
Bulk–Source
-0.30 V
Reverse bias
Bulk–Gate
2.98 V
—
Maximal (peak) absolute currents
Gate
16 µA
—
Bulk
43 µA
—
Drain/source
1.1 mA
Due to the main switch
Average absolute currents
Gate
290 nA
—
Bulk
5 µA
—
Drain/source
110 µA
—
Table 6.2: Simulated stress results for the transistors in the bootstrapped switch
Chapter 7
Conclusion
The various design and implementation details of the project, related to the goals
and limitations stated in sections 1.1 and 1.2 have been discussed in the preceding
chapters. In this section we provide an overview of the achievements of the thesis
work.
In chapter 2 analog multiplexers were discussed in general and several traditional approaches for realizing analog switches in CMOS technology were reviewed.
These simple realizations are not applicable for submicron CMOS implementation
with its accompanying low supply voltage and poor device characteristics. The
bootstrapping method was proposed at the end of the chapter as a means to circumvent the limitations imposed by the low supply voltage and a suitable circuit
of a bootstrapped switch was selected for further analysis and implementation.
Several possible methods for setting the DC voltage level of the AC coupled
video signals were reviewed in chapter 3. While all of the discussed architectures
were successfully used in analog video systems not all of them are appropriate for
realization in a submicron CMOS integrated circuit technology. A “stripped down”
version, consisting only of pull-up and pull-down transistors, of the commonly used
charge pump was selected for implementation and the trade-offs related to this
choice were discussed.
In chapter 5 we have given the important design considerations for the bootstrapped switch, the DC restore block and the possible hardware sharing between
these two circuits. The design trade-offs related to these circuits were discussed
and the transistor sizing and selection was given and motivated. Special attention was paid to the leakage currents in the bootstrapped switches, since in many
cases leakages are the factors dictating transistor sizing and type selection and,
therefore, limit the achievable performance.
Finally, in chapter 6 we provided a brief overview of the testbench that was used
for the simulations of the designed circuits. At the end of the chapter we presented
the achieved performance of the design and provided a detailed simulation results
regarding the performance of the final design.
57
Chapter 8
Future work
In order for an integrated circuit design to be fully characterized and declared to
be conforming to the specification, the physical layout have to be complete and
the extracted netlist simulated and verified. Despite that the completion of the
layout artwork for the designed blocks was set as desirable achievement for the
project, no block was finalized in the layout stage. This is the major direction for
future development of the designed blocks and towards completion of the video
AFE as a whole. The layout has to be completed in correspondence with the
overall floorplanning of the video AFE, the resulting extracted netlist has to be
simulated again and if necessary some of the design stages re-iterated in order to
regain any loss of performance.
While the main goal of performance and range of supported video formats
has been accomplished, this was achieved at the cost of suboptimal design in the
sense that the different formats have contradictory requirements. High resolution
formats require high bandwidth and linearity, while low resolution (usually TV
formats) require the bootstrapped switches to operate for long periods without
recharging. A possible future improvement of the design can be the separation
of the multiplexer inputs and the optimization of the inputs for specific video
formats. This will allow the required chip area to be minimized, mainly due to
the decreased size of the bootstrap capacitor.
The DC restoration circuit has been designed and verified to be functional but
no particular control strategy has been implemented. However, in order for an
actual algorithm to be devised, the design of the video ADC has to be completed
if it is to be included in the feedback loop for the measurement of the DC level.
Also, there could be several possible control algorithms with varying degree of
intelligence, therefore, they should be evaluated and the one which is most suitable
to the video AFE has to be selected.
59
Bibliography
[1] Roy Blake. Electronic communication systems. Delmar/Thomson Learning,
Albany, NY, USA, second edition, 2002.
[2] C. Lillebrekke, C. Wulff, and T. Ytterdal. Bootstrapped switch in low-voltage
digital 90nm cmos technology. In NORCHIP Conference, 2005. 23rd, pages
234 – 236, nov. 2005.
[3] J. Steensgaard. Bootstrapped low-voltage analog switches. In Circuits and
Systems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Symposium on, volume 2, pages 29 –32 vol.2, jul 1999.
[4] M. Waltari and K. Halonen. Bootstrapped switch without bulk effect in standard cmos technology. Electronics Letters, 38(12):555 – 557, 6 2002.
61
Appendix A
VerilogA code of the
binary-to-thermomenter
encoder
1
// V e ri lo g A f o r daisyVideoMux ,
daisyVideoMus_bin2therm_coder , v e r i l o g a
2
3 ‘include " c o n s t a n t s . vams "
4 ‘include " d i s c i p l i n e s . vams "
5
6 module daisyVideoMus_bin2therm_coder ( therm , vdd , vss , bin ,
_en , d i r , s i g n ) ;
7 output [ 0 : 3 0 ] therm ;
8 e l e c t r i c a l [ 0 : 3 0 ] therm ;
9 inout vdd ;
10 e l e c t r i c a l vdd ;
11 inout v s s ;
12 e l e c t r i c a l v s s ;
13 input [ 0 : 4 ] b i n ;
14 e l e c t r i c a l [ 0 : 4 ] b i n ;
15 input _en , s i g n ;
16 output d i r ;
17 e l e c t r i c a l _en , s i g n , d i r ;
18
19 parameter vThres = 0 . 5 5 ;
20 parameter t R i s e = 300p ;
21 parameter t F a l l = 300p ;
22 parameter r e a l vHigh = 1 . 1 ;
23
24 integer therm_tmp [ 0 : 3 0 ] ;
63
64
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VerilogA code of the binary-to-thermomenter encoder
integer i , inVal , dir_tmp ;
genvar j ;
a n a l o g begin
f o r ( i =0; i <31; i=i +1) begin
therm_tmp [ i ] = 0 ;
end
i n V a l =0;
f o r ( j =0; j <5; j=j +1) begin
i n V a l=i n V a l+ ( (V( b i n [ j ] )>vThres ) ? 1 : 0 ) ∗pow ( 2 , j ) ;
end
i f (V( s i g n )>=vThres ) begin
dir_tmp =1;
end
e l s e begin
dir_tmp =0;
end
f o r ( i =0; i <31; i=i +1)begin
i f ( inVal >0)begin
therm_tmp [ i ] = 1 ;
end
i n V a l=inVal −1;
i f (V( _en )>vThres ) begin
therm_tmp [ i ] = 1 ;
// dir_tmp =1;
dir_tmp =0;
end
end
f o r ( j =0; j <31; j=j +1) begin
V( therm [ j ] ) <+ t r a n s i t i o n ( therm_tmp [ j ] ∗
vHigh , 0 , t R i s e , t F a l l ) ;
end
V( d i r ) <+ t r a n s i t i o n ( dir_tmp ∗ vHigh , 0 , t R i s e , t F a l l ) ;
61
62
63 end
64 endmodule
Appendix B
VerilogA code of the video
signal generator
1
2
3
4
5
6
7
8
9
10
// V e ri lo g A f o r daisyVideoMux , d a i s y V i d e o G e n e r a t o r ,
veriloga
// G e n e r a t e s a v i d e o s i g n a l which can be used f o r
s i m u l a t i o n s of , f o r
// example , l i n e a r i t y , t i m i n g , e t c . . .
//
// A l l t i m i n g and s i g n a l l e v e l c h a r a c t e r i s t i c s can be chnged
from t h e
// c o r r e s p o n d i n g p a r a m e t e r s
//An a r b i t r a r y i n p u t s i g n a l can be f o r w a r d e d t o t h e o u t p u t
during the
// a c t i v e v i d e o p o r t i o n by s e t t i n g . i n p u t S e l e c t t o 1 .
//
//The i n p u t v O f f s e t can be used t o add a DC o f f s e t , n o i s e ,
etc , to the
// e n t i r e v i d e o s i g n a l
11
12
13 ‘include " c o n s t a n t s . vams "
14 ‘include " d i s c i p l i n e s . vams "
15
16 module d a i s y V i d e o G e n e r a t o r ( videoOut , hSync , blanc , vIn ,
vOffset ) ;
17
18 output videoOut , hSync , b l a n c ;
19 input vIn , v O f f s e t ;
20 e l e c t r i c a l videoOut , hSync , blanc , vIn , v O f f s e t ;
21
22 // This d e f a u l t p a r a m e t e r s s e t u p d o e s not n e c e s s a r i l y
65
66
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VerilogA code of the video signal generator
correspond to a
// m e a n i n g f u l v i d e o s i g n a l , i t i s j u s t good f o r c i r c u i t
simulation .
//=================================
// Timing p a r a m e t e r s
parameter r e a l hSync_period = 25 e−6 ;
parameter r e a l hSync_length = 2 e−6 ;
parameter r e a l f P o r c h _ l e n g t h = 3 e −6;
parameter r e a l bPorch_length = 4 e −6;
parameter r e a l p i x e l _ p e r i o d = 50 e −9;
//=================================
//=================================
// V o l t a g e l e v e l p a r a m e t e r s . These c o u l d be e a s i l y changed
t o IRE
// u n i t s , b u t v o l t s a r e more m e a n i n g f u l f o r c u r c u i t d e s i g n .
parameter r e a l vHigh = 1 . 1 , vLow = 0 ; // High / low o u t p u t
v o l t a g e s f o r t h e hSync and b l a n c o u t p u t s , t h e s e a r e
digital
parameter r e a l videoMax = 1 . 2 ;
//The h i g h e s t l e v e l found
in the a c t i v e video s i g n a l
parameter r e a l v i d e o B l a c k = 0 . 1 ;
//The b l a c k v i d e o
l e v e l , u s a l l y t h e same as b l a n k l e v e l , b u t not f o r NTSC
parameter r e a l v i d e o B l a n k = 0 . 0 ;
//The b l a n c i n g
level
parameter r e a l hSyncLevel = −0.35;
// hSync p u l s e
minimum l e v e l
parameter r e a l videoGain = 1 . 0 ; //The v i d e o s i g n a l ( not
o f f s e t ) i s m u l t i p i e d by t h i s
//=================================
parameter i n p u t S e l e c t =1; // s e t t o 1 t o s e l e c t e x t e r n a l
i n p u t , or t o 0
// t o s e l e c t i n t e r n a l l y g e n e r a t e d
random s i g n a l
integer hSyncActive , b l a n k A c t i v e , n ;
real activeVideo , video ;
integer s e e d ;
a n a l o g begin
@( i n i t i a l _ s t e p ) begin
hSyncActive = 0 ;
b l a n k A c t i v e =0;
67
57
s e e d =100;
58
end
59 i f ( a n a l y s i s ( " p s s " ) ) begin
60
V( videoOut ) <+2∗(V( vIn )+V( v O f f s e t ) ) ;
61
V( hSync )<+vLow ;
62
V( b l a n c ) <+vLow ;
63 end
64 e l s e begin
65
//@( t i m e r ( bPorch_length , hSync_period ) ) h S y n c A c t i v e
= 1 ;
66
n = ( ( $ a b s t i m e + hSync_length ) / hSync_period ) ;
67
@( t i m e r ( n∗ hSync_period ) ) ;
68
@( t i m e r ( n∗ hSync_period+hSync_length ) ) ;
69
//@( t i m e r ( b P o r c h _ l e n g t h+hSync_length , hSync_period ) )
hSyncActive = 0 ;
70
//@( t i m e r ( b P o r c h _ l e n g t h+hSync_length , hSync_period ) )
;
71
i f ( ( $abstime−bPorch_length>=n∗ hSync_period ) && (
$abstime−bPorch_length <=(n∗ hSync_period+
hSync_length ) ) ) begin
72
hSyncActive = 1 ;
73
end
74
e l s e begin
75
hSyncActive = 0 ;
76
end
77
78
79
80
//@( t i m e r ( 0 , hSync_period ) ) b l a n k A c t i v e =1;
81
//@( t i m e r ( b P o r c h _ l e n g t h+hS yn c _l en g th+f P o r c h _ l e n g t h ,
hSync_period ) ) b l a n k A c t i v e =0;
82
//@( t i m e r ( 0 , p i x e l _ p e r i o d ) ) a c t i v e V i d e o=
$ r d i s t _ u n i f o r m ( s e e d , v i d e o B l a c k , videoMax ) ;
83
n=(( $ a b s t i m e+bPorch_length+hSync_length+
f P o r c h _ l e n g t h ) / hSync_period +0.5) −1;
84
@( t i m e r ( n∗ hSync_period ) ) ;
85
@( t i m e r ( n∗ hSync_period+(bPorch_length+hSync_length+
fPorch_length ) ) ) ;
86
i f ( ( $abstime>=n∗ hSync_period ) && ( $abstime<=n∗
hSync_period+(bPorch_length+hSync_length+
f P o r c h _ l e n g t h ) ) ) begin
87
b l a n k A c t i v e =1;
88
end
89
e l s e begin
90
b l a n k A c t i v e =0;
91
end
68
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
//
//
VerilogA code of the video signal generator
i f ( inputSelect > 0.5) begin
a c t i v e V i d e o=V( vIn ) ;
end
v i d e o = ( t r a n s i t i o n ((1 − b l a n k A c t i v e ) , 0 . 0 , 2 4 0 p , 2 4 0 p ) ∗
a c t i v e V i d e o )+t r a n s i t i o n ( ( b l a n k A c t i v e ∗ v i d e o B l a n k )
, 0 . 0 , 2 4 0 p , 2 4 0 p )+t r a n s i t i o n ( ( hSyncActive ∗
hSyncLevel ) , 0 . 0 , 2 4 0 p , 2 4 0 p ) ;
//V( v i d e o O u t ) <+ t r a n s i t i o n ( vi d e oG a in ∗ v i d e o , 0 . 0 , 1 0 0 0
p ,1000 p ) ;
V( videoOut ) <+ 2∗ videoGain ∗ v i d e o ;
//V( v i d e o O u t ) <+ t r a n s i t i o n (V( v O f f s e t ) , 0 , 0 , 240p , 2 4 0
p) ;
V( videoOut ) <+ 2∗V( v O f f s e t ) ;
V( hSync ) <+ t r a n s i t i o n ( hSyncActive==1 ? vHigh : vLow
, 0.0 ,
240p , 240p ) ;
V( b l a n c ) <+ t r a n s i t i o n ( b l a n k A c t i v e==1 ? vHigh : vLow
, 0.0 ,
240p , 240p ) ;
//V( b l a n c )<+n ;
end // e l s e
end
endmodule
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© Pavel Angelov