Download Modeling of low voltage nanometer

Modeling of Low-Voltage Nanometer Merged MOS Devices
V. Rakitin
F. V. Lukin Scientific Physical Problem Research Institute , Moscow, [email protected]
Abstract – This paper presents the simulation of the electrical characteristics of new type of low-voltage nanometersized devices concept called the merged MOS transistor (MMOS). The design and operation are described. The MMOS
with a minimum topological size of 10 nm is simulated and shown operating at supply voltage of no less than 0.1V.
1. INTRODUCTION
Various physical, technological, design and circuit engineering techniques can be used to reduce the
relative sizes of semiconductor devices and to lower power supply voltage [1]. Some are already being
researched and implemented: SOI CMOS, multi-gate (MG MOS, FINFET), nanowire (NW MOS) [2],
Schottky barrier (SB MOS) [3], tunnel field effect (TFET) [4], etc. To reduce the supply voltage various
operation modes may be used: subthreshold, bulk forward biasing, adaptive biasing, dynamic change of
power, etc. Transition to three-dimensional structures may increase the density of elements. Thus a vertical
nanowire gate-all-around (GAA) MOSFET occupies minimal area.
Merged MOS transistors (MMOS) are designed for low supply voltage, which permits the creation
of the most compact structure of devices and circuits [5].
The purpose of this paper is the modeling of low voltage nanometer merged MOS devices
2. MMOS CONSTRUCTION AND OPERATION
Merged devices are well known, and some of them are widespread occurrence. For example, a fourlayer p-n-p-n device (SCR) may be regarded as a combination of a n-p-n bipolar transistor with a p-n-p
transistor.
Fig.1 Cross-section dual-gate nanometer MMOS with p-n junctions
The basic idea of MMOS is the merging of active domains of n-channel and p-channel MOS
transistors (Fig 1). Gates and channels may be common. The latter makes sense if the conductivity of the
active region is close to the intrinsic conductivity of silicon (or if the background impurity concentration is
about 1e13 – 1e14 cm-3). Notably, the movement towards to the undoped channels is a general trend of
nanometer MOS technology.
The MMOS must contain a source of electrons and holes – merged source. The MMOS must contain
a merged drain, which absorbs both types of carriers (Fig 1). A p-n junction, where the n+ region is at null
potential, and the p+ region is at supply voltage Vs, is used as a merged source. At low voltages (Vs ≤ 0.6 V)
p-n junction direct current is much less than transistor channels operating current.
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The MMOS may be considered as two MOS transistors: one n-channel and one p-channel, and the
MMOS itself as amplifier, with the input electrode as a gate, and the output electrode as a merged drain.
The middlezone metal gate MMOS (4.65 eV work function) is symmetric device. The electron and
hole concentrations (as well as electron and hole currents) of the symmetric MMOS are approximately equal
(Fig 2).
Fig 2: The density of electrons (a), holes (b), and the current(c) in the MMOS (at Vg=Vd=Vs/2=0.2 V)
If the gate voltage is close to the supply voltage (Vg = Vs), the concentration of electrons and the
electron current dominate (Fig 3).
Fig 3: The density of electrons (a), holes (b), and electron current(c) (at Vg=Vd=Vs=0.4 V)
The presence of electronic conductivity between the n+ source and the n+ drain aligns their potential
and the MMOS output becomes null potential.
At the zero gate voltage the concentration of holes in the channel is high and the output potential is
close to Vs. Thus, a basic MMOS acts as an inverting amplifier.
The MMOS contains a forward-biased p-n junction (similar to CMOS with a direct displacement of
the substrate), which causes direct diode current. Therefore, the relation of this current to MMOS operating
current is fundamental. Fig 4 shows the MMOS current limited by the active load of the supply voltage
circuits. It follows from Fig 4, that the value of MMOS operating current (which determines its speed) can be
greater than the diode current by five to six orders of magnitude.
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Fig 4: The ratio of currents of the MMOS and the parasitic diode
MMOS are allowed for a wide variety of designs: single gate and multi-gate, vertical and horizontal
channels, planar and three-dimensional structure. MMOS with GAA can be created from nanowire.
P-n junctions, Schottky contacts, tunnel junctions, etc. may be used as the merged source/drain.
Particularly, the source can be a part of an area where carriers of both types are generated locally (e.g.
photogeneration area).
MMOS may be used in both linear and digital circuits. The implementation of complex logic
functions is achieved by summation of gate potentials or summation of drain currents. The multi-gate
configurations may also be used.
3. NANOMETER MMOS MODEL
The nanometer MMOS modeling was performed by using DESSIS module of the ISE TCAD
program package. Fig 1 shows a vertical MMOS, but the results are also valid for horizontal MMOS. The
transistor body thickness ranges from 10 to 20 nm; gate length – from 40 to 100 nm; the effective thickness
dielectric (silicon oxide) – from 1 to 2 nm. The transistor body width is 1 micron. The background impurities
concentration is 1e13 cm-3. The recombination of carriers was taken into account by using the ShockleyReed-Hall mechanism. The minority carriers lifetime ranges from 10 to 100 ms and the surface
recombination velocity ranges from 1e3 to 1e4 cm/s. The lows of these values are typical for conventional
integrated appliances and are set in DESSIS by default. Both the p-n junction and the Schottky contacts are
used in merged source/drain. In the first case, the used dopants are arsenic (n+ region) and boron (p + region)
with concentration of 1e19 cm-3 for each type of impurity. In the second case, the Schottky contact
parameters are defined by the metal work function. MMOS drains are combined to one another directly by
overlapping the highly doped areas or by using a conductive connection. The n+source and p+source are
separated and the area between them serves as the merged source. Metals with a work function ranged from
4.1 eV to 5.2 eV are considered as materials for the gate.
When simulating a simple inverting amplifier MMOS the gates have been connected. In other cases,
they were controlled independently or in accordance with the connection circuit. Additional gates were
introduced for the analysis of more complex elements. Main static characteristics have been modeled; small
signal parameters have been calculated; transients have been analyzed.
The following simulating results belong MMOS, whose the geometrical dimensions are the
same as in Fig 1.
4. SYMMETRICAL MMOS CHARACTERISTICS
The main static characteristics of the symmetric MMOS with supply voltage Vs = 0.6 V are given
for consideration.
The input characteristic of a basic MMOS – the dependence of drain current (Id) versus the gate
voltage (Vg) at fixed drain voltage (Vd=0.3V) is shown in Fig 5a.
It differs from the characteristics of an ordinary MOS in the fact that the operating current changes
its direction depending on the gate voltage. At voltages greater than half the supply voltage, the current flows
into the device, but at lower voltages it flows out of it. Fig 5a shows the direct current (Is) few orders of
magnitude lower than the operating current.
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Fig 5: Input (a) and output (b) characteristics of the MMOS
The set of MMOS output characteristics (built with an incremental step of 0.1 V) shown in fig 5b is a
superposition of -n and p-channel transistor I-V curves.
The value range of negative and positive currents is defined by the metal work function of the gate.
The maximum effective gate voltage of a symmetric MMOS is half the supply voltage, i.e.
significantly lower than any of CMOS transistors has. In fact the MMOS currents are subthreshold and their
amounts are relatively small which is a fee for low supply voltage. The supply voltage drop causes the
operational and direct currents to decrease exponentially, as shown in Fig 6.
Fig 6: Dependence of operating and direct currents on MMOS supply voltage Vs
5. SIMULATION AND PERFORMANCE OF ASYMMETRIC MMOS
The usage of asymmetric MMOS (a-MMOS) may significantly increase the amount of operating
currents. Various metals with different work functions were used as gate materials in a-MMOS.
The influence of the gate work function has been studied; the suitable MMOS design has been
chosen (gate 1 and 2 material work functions are 4.3 eV and 5.0 eV respectively).
In this case, the electrons are localized within gate 1, and the holes - within gate 2 (Fig 7).
Fig 7: The density of carriers (a) and currents (b) where Vg=0 and Vg=Vs/2=0.2 V (c)
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The carrier concentration and current density become significantly greater as shown in Fig 7
The MMOS operating current increase is due to a reduction of the barrier between the source and
channel. Since the barrier gap between n+ and p+ sources does not change, the amount of direct current
remains the same (Fig 8). However, there is a parasitic leakage current (between the drain and source), which
is particularly significant at low supply voltages.
Fig 8: Operating (1), leakage (2) and direct currents (3) in a-MMOS.
The results of simulating output and transfer characteristics of an a-MMOS at supply voltage of 0.4 0.1 V are shown in Fig 9 (the scale is partially shown).
Transfer characteristics allow us to estimate the MMOS voltage gain factor, which is about 10, and
may be increased by an order of magnitude through sophistication of the design (by adding a second gate
layer that converts MMOS to the cascode amplifier).
The simulation results show that it should be possible to use the a-MMOS in analog and digital
circuits with supply voltage significantly reduced up to 0.2 V. The strong deterioration of the MMOS
amplifying properties at a supply voltage of less than 0.1 V is due to the presence of significant leakage
currents.
Fig 9: Output (a) and transfer (b) characteristics of the a-MMOS
The MMOS dynamic characteristics in high-signal mode have been simulated with an external load
of about 1 fF (MMOS gate capacitance is about 0.2 fF). In such circumstances the MMOS satisfactorily
transmits the pulse sequence with a frequency of 10 GHz at a supply voltage of 0.6 V (Fig 10a). The MMOS
switching delay is less than 20 ps and it grows linearly with the increase of capacitance load. The operating
frequency is reduced to 100 MHz at supply voltage of 0.2 V (Fig 10b).
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Fig 10: Transients in the MMOS: Vs=0.6 V (a), Vs=0.2 V (b)
6. CONCLUSION
The modeling of the various MMOS designs demonstrates them operating at nanometer dimension
level. The MMOS simulating with the minimal topological size of 10 nm has been made. The simulating
results show that the basic MMOS keeps operating even at supply voltages near 0.1 V. It has voltage gain
factor of 10 and above. Also it can operate at gigahertz frequencies.
The MMOS parameters are sufficient for digital and analog schemes implementation where the size
minimization under low supply voltage and high-speed performance are crucial.
REFERENCES
1. A. S. Hanson et al. "Ultralow-voltage, minimum-energy CMOS", IBM J. Res. & Dev., 50, pp.469-490,
2006
2. J. Appenzeller et al. "Toward Nanowire Electronics", IEEE Tran. ED, 55, pp. 2827 2845 2008
3. J. Larson et al., "Overview and Status of Metal S / D Schottky-Barrier MOSFET Technology", IEEE Tans.
ED., 53, pp.1048-1058, 2006
4. A. Seabaugh et al. "Low-Voltage Tunnel Transistors for CMOS", Proc. IEEE, 98, pp.2095-2110, 2010
5. V. Rakitin, "Merged transistors", Electronics Industry, pp.59-63, 2004