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EE2174: Digital Logic and
Lab
Professor Shiyan Hu
Department of Electrical and Computer Engineering
Michigan Technological University
Combinational Circuit
Overview
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Combinatorial Circuits
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Definition
Divide and Conquer
Three Design Methodologies
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Gate Library Based Design
Full Customer Design
Programmable Logic Array Based Design
Combinational Logic
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Combinational Circuits
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A combinational circuit consists of logic
gates whose outputs, at any time, are
determined by combining the values of
the inputs.
For n input variables, there are 2n
possible binary input combinations.
For each binary combination of the
input variables, there is one possible
output.
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Combinational Logic
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Combinational Circuits (cont.)
Hence, a combinational circuit can be
described by:
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1.
2.
A truth table that lists the output values for
each combination of the input variables, or
m Boolean functions, one for each output
variable.
n-inputs
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••
•
Combinational
Circuit
Combinational Logic
••
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m-outputs
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Combinational vs. Sequential Circuits
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Combinational circuits are memory-less.
Thus, the output value depends ONLY on the
current input values.
Sequential circuits consist of combinational
logic as well as memory elements (used to
store certain circuit states). Outputs
depend on BOTH current input values and
previous input values (kept in the storage
elements).
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Combinational Logic
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Combinational vs. Sequential Circuits
n-inputs
Combinational
Circuit
m-outputs
(Depend only on inputs)
Combinational Circuit
n-inputs
Combinational
Circuit
m-outputs
Next
state
Storage
Elements
Present
state
Sequential Circuit
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Combinational Logic
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Important Design Concepts
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Modern digital design deals with various
methods and tools that are used to design and
verify complex circuits and systems.
Important concepts:
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Design Hierarchy
Top-Down and Bottom-Up Design
Computer-Aided-Design (CAD) tools
Hardware Description Languages (HDLs)
Logic Synthesis
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Combinational Logic
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Design Hierarchy
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“Divide-and-Conquer” approach used to
cope with the challenges of designing
complex circuits and systems (many times
in the order of millions of gates).
Circuit is broken into blocks, repetitively.
Challenge: Verify that the block-based
circuit performs its intended function.
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Combinational Logic
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Design Hierarchy
Example: 9-input odd function
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Combinational Logic
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Why is Hierarchy useful?
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Reduces the complexity required to
design and represent the overall
schematic of the circuit.
Reuse of blocks is possible. Identical
blocks can be used in various places in a
design, or in different designs.
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Combinational Logic
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Top-Down Design
Gajski and Kuhn’s Y Chart
Behavioral
Top-Down
Architectural
Structural
Algorithmic
Functional Block
Processor
Systems
Hardware Modules
Logic
Algorithms
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transistors
Transfer Functions
Rectangles
Cell, Module Plans
Floor Plans
Bottom-Up
Clusters
Physical Partitions
Physical/Geometry
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Combinational Logic
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Reusable Functions and CAD
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Whenever possible, we try to decompose a complex design
into common, reusable function blocks
These blocks are
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verified and well-documented
placed in libraries for future use
Representative Computer-Aided Design Tools:
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Schematic Capture
Logic Simulators
Timing Verifiers
Hardware Description Languages
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Verilog and VHDL
Logic Synthesizers
Integrated Circuit Layout
Combinational Logic
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Top-Down versus Bottom-Up
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A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks and
combines them into larger and more complex functional
blocks
Designs usually proceed from both directions simultaneously
 Top-down design answers: What are we building?
 Bottom-up design answers: How do we build it?
Top-down controls complexity while bottom-up focuses on
the details
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Combinational Logic
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Integrated Circuits
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Integrated circuit (informally, a “chip”) is a
semiconductor crystal (most often silicon) containing
the electronic components for the digital gates and
storage elements which are interconnected on the
chip.
Terminology - Levels of chip integration
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SSI (small-scale integrated) - fewer than 10 gates
MSI (medium-scale integrated) - 10 to 100 gates
LSI (large-scale integrated) - 100 to thousands of gates
VLSI (very large-scale integrated) - thousands to 100s of
millions of gates
Combinational Logic
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Technology Parameters
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Specific gate implementation technologies are characterized by
the following parameters:
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Fan-in – the number of inputs available on a gate
Fan-out – the number of standard loads driven by a gate output
Logic Levels – the signal value ranges for 1 and 0 on the inputs and 1
and 0 on the outputs (see Figure 1-1)
Noise Margin – the maximum external noise voltage superimposed
on a normal input value that will not cause an undesirable change in
the circuit output
Cost for a gate - a measure of the contribution by the gate to the
cost of the integrated circuit
Propagation Delay – The time required for a change in the value of a
signal to propagate from an input to an output
Power Dissipation – the amount of power drawn from the power
supply and consumed by the gate
Combinational Logic
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Propagation Delay
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Propagation delay is the time for a change on an input of a gate
to propagate to the output.
Delay is usually measured at the 50% point with respect to the
H and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal changes
may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are defined
with respect to the output, not the input.
An HL input transition causes:
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an LH output transition if the gate inverts and
an HL output transition if the gate does not invert.
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Combinational Logic
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Propagation Delay Example
OUT (volts)
IN (volts)
 Find tPHL, tPLH and tpd for the signals given
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1.0 ns per division
Combinational Logic
t (ns)
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Fan-out
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Fan-out can be defined in terms of a standard
load
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Example: 1 standard load equals the load
contributed by the input of 1 inverter.
Transition time -the time required for the gate
output to change from H to L, tHL, or from L to H,
tLH
The maximum fan-out that can be driven by a gate
is the number of standard loads the gate can drive
without exceeding its specified maximum
transition time
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Combinational Logic
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Fan-out and Delay
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The fan-out loading a gate’s output affects
the gate’s propagation delay
Example:
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One realistic equation for tpd for a NAND gate
with 4 inputs is:
tpd = 0.07 + 0.021 SL ns
SL is the number of standard loads the gate is
driving, i. e., its fan-out in standard loads
For SL = 4.5, tpd = 0.165 ns
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Combinational Logic
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Cost
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In an integrated circuit:
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The cost of a gate is proportional to the chip area occupied
by the gate
The gate area is roughly proportional to the number and size
of the transistors and the amount of wiring connecting them
Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
So gate input count is a rough measure of gate cost
If the actual chip layout area occupied by the gate is
known, it is a far more accurate measure
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Combinational Logic
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Chip Design Styles
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Full custom - the entire design of the chip down to the smallest detail
of the layout is performed
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Standard cell - blocks have been design ahead of time or as part of
previous designs
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Expensive
Justifiable only for dense, fast chips with high sales volume
Intermediate cost
Less density and speed compared to full custom
Gate array - regular patterns of gate transistors that can be used in
many designs built into chip - only the interconnections between gates
are specific to a design
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Lowest cost
Less density compared to full custom and standard cell
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Combinational Logic
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Gate Library Based Design
Methodology
Specification
1.
Write a specification for the circuit if one is not already
available
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Formulation
2.
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Derive a truth table or initial Boolean equations that
define the required relationships between the inputs and
outputs, if not in the specification
Optimization
3.
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Apply K-map and other optimizations
Draw a logic diagram or provide a netlist for the resulting
circuit using ANDs, ORs, and inverters
Combinational Logic
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Design Procedure
4.
Technology Mapping
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5.
Map the logic diagram or netlist to the
implementation technology selected
Convert to CMOS
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Replace each gate by its CMOS
implementations
Combinational Logic
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Design Example
1.
Specification
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BCD to Excess-3 code converter
Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to
each BCD code word
Implementation:
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multiple-level circuit
NAND gates (including inverters)
Combinational Logic
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Design Example (continued)
Formulation
2.
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Conversion of 4-bit codes can be most easily
formulated by a truth table
Variables
- BCD:
Input BCD
Output Excess-3
A,B,C,D
ABCD
WXYZ
Variables
0000
0011
- Excess-3
W,X,Y,Z
0001
0100
0010
0101
Don’t Cares
- BCD 1010
0011
0110
to 1111
0100
0111
0101
0110
0111
1000
1001
Combinational Logic
1000
1001
1010
1011
110 0
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Design Example (continued)
3.
Optimization
a.
z
2-level using
K-maps
A
W = A + BC + BD
X = B C + B D + BC D
Y = CD + C D
x
Z= D
C
1
y
1
0
1
3
4
5
7
1
X
X
12
13
8
9
X
X
1
B
1
4
5
A
X
X
12
13
8
9
1
1
0
4
5
7
6
4
1
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1
1
X
13
1
X
10
C
2
8
B
14
11
w
3
A
X
D
1
12
6
X
0
X
7
15
1
10
C
X
2
X
D
1
3
1
X
14
11
0
1
6
15
1
1
2
1
X
C
X
15
X
9
11
Combinational Logic
D
B
X
14
10
1
X
1
1
8
7
X
13
6
X
15
X
9
2
1
5
12
A
X
3
11
14
X
10
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B
Design Example (continued)
3.
Optimization (continued)
b.
Multiple-level using transformations
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D
Perform extraction, finding factor:
W = A + BC + BD
X = B C + BD + B CD
Y = CD + C D
Z=
T1 = C + D
W = A + BT1
X = B T1 + B C D
Y = CD + C D
Z= D
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Combinational Logic
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Design Example (continued)
3.
Optimization (continued)
b.
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Multiple-level using transformations
T1 = C + D
W = A + BT1
X = BT1 + B CD
Y = CD +
CD
Z =
D
An additional extraction not shown in the text since it uses
a Boolean transformation: (CD = C + D = T1 ):
W = A + BT1
X = B T1 + B T1
Y = CD + T
1
Z=
D
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Combinational Logic
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Design Example (continued)
4.
Technology Mapping
•
Mapping with a library containing inverters and 2input NAND, 2-input NOR, and 2-2 AOI gates
A
A
W
B
W
X
B
X
C
Y
C
D
D
Y
Z
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Combinational Logic
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Z
Design Example (continued)
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5. Convert to CMOS through replacing
each gate to its CMOS implementation
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Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5)
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Technology Mapping
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Mapping Techniques
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NAND gates
NOR gates
MUX gates
Multiple gate types
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Combinational Logic
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Mapping to NAND gates
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Assumptions:
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Gate loading and delay are ignored
Cell library contains an inverter and n-input NAND gates, n =
2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
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Replacing AND and OR symbols,
Pushing inverters through circuit fan-out points, and
Canceling inverter pairs
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Combinational Logic
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NAND Mapping Algorithm
Replace ANDs and ORs:
1.
.
.
.
.
.
.
.
.
.
.
.
.
Repeat the following pair of actions until
there is at most one inverter between :
2.
a.
b.
A circuit input or driving NAND gate output, and
The attached NAND gate inputs.
.
.
.
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Combinational Logic
.
.
.
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NAND Mapping Example
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Combinational Logic
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Full Custom Design Methodology
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Similar to the CMOS implementation for Combinational Gate
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Combinational
Logic
Programmable Logic Array
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The set of functions to be implemented is first transformed to
product terms
Since output inversion is available, terms can implement either a
function or its complement
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Combinational
Logic
Programmable Logic Array
Example
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To implement
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F1= A’B’C+A’BC’+AB’C’=(AB+AC+BC+A’B’C’)’
F2=AB+AC+BC
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Combinational
Logic
Programmable Logic Array
Example
A
B
C
X
X
X
1
X
X
X
2
X
X
X Fuse intact
Fuse blown
X
X
X
3
X
X
4
X
X
X
X
C C B B A A
0
X
1
F1
F2
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Combinational
Logic
Summary
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Three design styles
Full custom design
 Gate library based design
 PLA based design

2017/5/23
PJF- 39
Combinational
Logic