Download A1A2A3= 000 001 010 011 100 101 110 111

UNIVERSITY OF CALIFORNIA, DAVIS
Department of Electrical and Computer Engineering
EEC180A
DIGITAL SYSTEMS I
Winter 2015
LAB 3: COMBINATIONAL NETWORK DESIGN
The purpose of this lab is to learn how to design a simple combinational logic network.
Hardware Required:
2
74LS00 Quad 2-input NAND gate
2
74LS04 Hex INVERTER
3
74LS10 Triple 3-input NAND gate
1
74LS163 Synchronous Binary Counter
1
7-segment display and seven current-limiting resistors
Preparation (Pre-lab)
 Do the complete paper design of the NAND-NAND implementation of the combinational
network specified in the lab write-up. Your paper design must include the following
items:
o K-maps for each of the 7 output signals
o Minimized sum of products (SOP) equation for each output
o Circuit representation using gates (i.e. schematic diagram) for the complete
network using 3-input NAND gates, 2-input NAND gates, inverters and a
74LS163 binary counter.
Description
a) In this lab, you will design a circuit to display the pattern shown below on a sevensegment display. The circuit uses 3 binary inputs, A1, A2, and A3, to produce eight
different outputs on the seven-segment display. You will use the 74LS163A to generate
the 3-bit binary input. Your 7-segment display should be configured for active-low
operation. That is, a low voltage will turn on an LED segment while a high voltage will
turn the segment off. Therefore, your circuit outputs will be active-low. You must use a
current-limiting resistor for each of the seven LED segments so that the maximum IOL
specification for the chips that generate the output signals is not exceeded.
Animation pattern: (dark segment = “LED on”, light segment = “LED off”)
X1
X6
X7
X5
A1A2A3= 000 001 010 011 100 101 110
111
X2
X3
X4
b) Design two combinational networks which satisfy the specification given in part a:
1. Using 3-input NAND gates, 2-input NAND gates and inverters. This design will be
based on the minimum SOP equations.
2. Using 4-input, 3-input, or 2-input NOR gates and inverters. This design will be based
on the minimum product of sums (POS) equations.
c) Enter both of your designs schematics in Quartus II and verify your designs by
simulating them in Modelsim-Altera.
1) Group your input signal with the Combine Signals option in the wave viewer.
Highlight the input signals (A1, A2, A3) by holding the shift key down as you select
each one; right click and select Combine Signals. The result name could be
something like A1A2A3, and the radix can be set to binary. Make sure your MSB
(A1) is on top, by selecting Top Down or Top up to reverse the order of the bits, if
necessary. Also, group X7 to X0 and let X7 as MSB, then set the radix to binary.
2) Drive values of the input A1A2A3 with the Force command and simulate in steps of
1000ns. You should observe a timing diagram similar to the one in Fig. 1.
Figure 1. Simulation Output.
3) Demonstrate you can simulate the circuit in ModelSim. Have your TA sign your lab
verification sheet.
d) Build and test your SOP circuit version using NAND gates and inverters. Note that you
are limited to the number of parts specified in the “Hardware Required” list above.
1) Use the 74LS163 counter to drive the inputs to your circuit.
2) Demonstrate your circuit's operation. Have your TA sign your lab verification sheet.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements" document available on the class web page. Be sure to include the
following items in your lab report:

Lab cover sheet with TA verification for circuit simulation and performance

Graded pre-lab

Altera schematics for the two combinational networks

Simulation waveforms for the two combinational networks

Complete paper design for the NOR-NOR network including K-maps and minimized
product of sums (POS) equations for each of the output signals.

Complete paper design for the NAND-NAND network including K-maps and minimized
SOP equations for each output signal. (You can use your pre-lab if it was entirely
correct.)

Show your calculations for the current-limiting resistors so that the maximum IOL
specification for the chips that generate the output signals is not exceeded.
Grading
Prelab
10 points
Lab checkoff
30 points
Lab report
60 points