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ECE 6332 Design Project Proposal: VDD Stacking by Wenlu Sun & Jiyati Verma Problem In moving from 2-D to 3-D lithographic techniques, a couple major challenges had to be overcome before the process could be industrialized. The first challenge had to do with power dissipated by the 3-D structure that contained active elements. But research leading to the development of methods for on-chip thermal analysis and new techniques for thermal optimization in 3D ICs has mostly alleviated this problem. The second challenge is I/O pin limitation problem: even though the number of I/O pins remains the same from design to design, the amount of power dissipated per pin increases for more advanced technologies. As the technology scales down, technology generations lose their tolerance for noise. Our project will focus on comparing 2-level stacked circuits, with different combinations of a single AND, OR, and NOT gate in each block. Approach Fig. 1 : A schematic of a 2-level stacked-VDD 1 Figure 2. Comparison of conventional and two-story power delivery sheme.2 To compare different setups of 2-level stacked circuits, we will explore 6 combinations: NOT & NAND, NOT & NOR, NOT & XOR, NAND & NOR, NAND & XOR, and NOR & XOR. This way we can explore how to deal with not only transistors, but also with transmission gates (XOR uses a transmission gate). We will not be using level shifters in our analysis, we would assume Body effect and subthreshold leakage. For each circuit we would analyze the worst case input transitions, and calculate power dissipated for the best voltage regulator. The IR and Ldi/dt noise in the power delivery network is not directly determined by power, but by the current delivered to the circuit. In VDD-stacking paradigm (see Fig. 1), logic blocks are stacked several levels high and power is delivered to the circuit as multiples of the regular supply voltage VDD. The advantage of this new circuit structure is that the current requirements between logic blocks operating in different VDD domains are balanced, so the current flowing through each external power grid will be reduced to 1/n of the original value (see Fig. 2). Therefore, the noise issue will be significantly alleviated. But in the case where the currents in each domain are not well balanced, the currents flowing through the external power grids will increase and worsen the IR and Ldi/dt noise. If time permits, we will certainly expand our analysis. For example, we could observe whether the power dissipated gets reduced by where the NOT gate is placed (closer to 2VDD or ground). We could also study the schematic structure of M-stage Binary adder, simulate it in Cadence, get data of the voltage noise with high frequency or low frequency. Depending on the do-ability of these sub-problems, we can increase the complexity of our approach if need be, by further analyzing whether gates in parallel or in series dissipate more or less power. For preliminary simulations, we’ve looked at the effect of putting 3 inverters in series and parallel on the noise reduction. Design We would design everything from the gates to the layouts in the Virtuoso atmosphere. For each pair of logic gates, we will design and see what type of voltage regulator would be appropriate for each pair of logic gates, on a power consumption basis. The purpose of the different voltage regulators would be to balance current locally, for each sub-circuit. For all the comparisons, we will keep the sizing the same in each gates so that we can make more true-to-the-fact comparisons. Hopefully developing voltage regulators with our own imagination will ensure the that our design is novel. Timeline 10/21: complete preliminary simulations on Cadence of parallel & series NOT, NAND, NOR, and XOR gates 10/24: (1) NOT & NAND simulations 10/28: (2) NOT & NOR simulations 10/31: (3) NOT & XOR simulations 11/04: (4) NAND & NOR simulations 11/07: (5) NAND & XOR simulations 11/11: (6) NOR & XOR simulations 11/14: Expansion or completion of core goals 11/21: Analysis Figure 7 : The pairs of gates up for analysis 11/25: Thanksgiving circuit structure 11/28: Analysis & Documentation 12/01: Final Report and Presentation due We plan on doing everything 50/50. Project Status We studied the basic idea of VDD-stacking and the way it works. To further test it, we have done some very initial simulation of a 3-bit inverter, Fig. 3 shows the schematic structure, basically, the three inverters share the same power supply and work independently, to model the noise due to IR and Ldi/dt, we included a resistance and an inductance for the power supply. Fig. 4 shows the floating of VDD when all three inverters work in same phase (input: 01), and it shows a significant noise ~0.09 V during this single transition for the middle inverter. Then we designed a 3-bit stacked inverter shown in Fig. 5, the results in Fig. 6 show that, when all three inverters work again in the same phase, the noise floating is only < 0.04 V for the middle inverter. Figure 3. The schematic structure of 3-bit parallel inverters. Figure 4. Floating of VDD in transition 01 for the 3-bit inverters. Figure 5. The schematic structure of stacked 3-bit inverter. Figure 6. Floating of power supply for the middle inverter in transition 01. Bibliography 1. Y. Zhan, S. S. Sapatnekar, “Automated Module Assignment in Stacked- VDD designs for highefficiency power delivery” in ACM Journal on Emerging Technologies in Computing Systems, Vol. 4, Issue 4, October 2008. 2. J. Gu, C. H. Kim, “Multi-Story power delivery for supply noise reduction and low voltage operation” in Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISLPED), August 2005. 3. A. C. Cabe, Z. Qi, M. R. Stan, “Stacking SRAM Banks for Ultra Low Power Standby Mode Operation”, Design Automation Conference (DAC), June 13-18, 2010. 4. W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, Y. Tsai, “Total Power Optimization through Simultaneously Multiple- VDD Multiple-VT Assignment and Device Sizing with Stack Forcing”, in Proceedings of the 2004 International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2004. 5. Y. Zhan, T. Zhang, S. S. Sapatnekar, “Module Assignment for Pin-Limited Designs under the Stacked-VDD Paradigm”, Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2007.