Download Combinational Logic

Combinational Circuits
(Continued)
(Materials taken primarily from:
http://sites.google.com/site/ece3724/ and
http://www.cs.Princeton.EDU/~cos126 )
Summary of Last Lecture
• Digital signals are binary (0 or I)
• Binary values can be viewed as logic values:
– digital signals treated as logic propositions
– digital circuits treated as functions and represented as Boolean
expressions and truth tables
• Sum-of-Product (SOP) Boolean expressions can be formed from a truth
table
• Digital circuits are made from assemblies of logic gates: AND, OR, NOT,
NAND, XOR…
• Each Boolean expression specifies a combinatorial digital circuit built using
logic gates
– gates correspond to logic operators
• The axioms of Boolean algebra can be used to simplify Boolean
expressions
– Karnaugh Maps “automate” this process
– Used to optimize circuit design
Example 1
• Odd Parity
– 1 if odd number of inputs are 1
– 0 otherwise
• Using Logisim
Adder
• Build a 4-bit adder: 9 inputs, 4 outputs
Truth Table
• Fuller adder is to big: 29 rows!
Revised Adder
• Design 1 bit at a time
– Chain together 1-bit adders to make
a 4-bit adder
• Design carry bit and sum bit
circuits separately
4-Bit Adder
Sum
1-Bit Adder
4-Bit Adder
Carry
Logisim Model
From Gates to Switches
OR gate:
From Gates to Switches
AND gate:
Switch Inputs
High True switch
Vdd
Vdd
L
Vdd is power
supply voltage,
typically 5V or
3.3V
H
Gnd is 0 V
Gnd
Switch open
(negated), output is L
Gnd
Switch closed ((asserted),
),
output is H
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35
Examples of high, low signals
Vdd
Vdd
Low True switch
H
L
Gnd
Switch open (negated),
output is H
Gnd
Switch closed ((asserted),
),
output is L
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36
CMOS transistors (P, N)
S: source
G: gate
D: drain
transistor
operation of P, N
types is
complementary
to each other
Copyright 2005. Thomson/Delmar Learning, All rights
reserved.
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37
Inverter gate - takes 2 transistors
PMOS is open (off)
NMOS is Closed (on)
PMOS is closed (on)
NMOS is Open (off)
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reserved.
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38
Buffer - takes 4 transistors
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reserved.
In digital logic,
logic NMOS must be connected to ground,
ground PMOS to
VDD.
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NAND gate - takes 4 transistors
AB Y
L L H
L H H
H L H
H H L
AB
0 0
0 1
1 0
1 1
Y
1
1
1
0
out
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Another logic gate - takes 4 transistors
AB
0 0
0 1
1 0
1 1
Y
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How do we make an AND gate?
The only
Th
l way with
i h CMOS transistors
i
iis to connect an iinverter
after a NAND gate.
Copyright 2005. Thomson/Delmar Learning, All rights
reserved.
Takes 6 transistors! In CMOS technology, NAND gates are
preferable to AND gates because they take less transistors, are
faster, and consume less power.
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42
Combinational Building Blocks, Mux
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reserved.
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45
Binaryy Adder
F (A,B,C) = A xor B xor C
G = AB + AC + BC
These equations look familiar. These define a Binary Full
Adder :
A B
Cout
A
B
Co
Ci
Sum = A xor B xor Cin
Cin
Cout = AB + Cin A + Cin B
= AB + Cin (A + B)
S
Full Adder (FA)
Sum
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46
4 Bit Ripple Carry Adder
A(3) B(3)
Cout C(4) A
B
Co
Ci
A(2) B(2)
C(3)
A
B
Co
Ci
A(1) B(1)
C(2)
A
B
Co
Ci
S
S
S
Sum(3)
Sum(2)
Sum(1)
A(0) B(0)
C(1)
A
B
Co
Ci
C(0)
Cin
S
Sum(0)
A[3:0]
[ ]
B[3:0]
+
SUM[3:0]
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Incrementer
A(3)
A(2)
A(1)
A(0)
EN
xor
xor
xor
xor
Y(3)
Y(2)
Y(1)
Y(0)
A[3:0]
inc
Y[3:0]
If EN = 1 th
then Y = A + 1
If EN = 0 then Y = A
EN
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48
Combinational Right Shifter
A combinational block that can either shift right or pass data
unchanged
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reserved.
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49
ALU Overview
ALU Interface.
• Add, subtract, bitwise and, bitwise xor, shift left, shift right,
copy.
• Associate 3-bit integer with 5 primary ALU operations.
- ALU performs operations in parallel
-control wires select which result ALU outputs
ALU Implementation