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Introduction to Computer Architecture
Lecture 2 – Digital Logic Design
August 20th, 2008
www.qatar.cmu.edu
Computer Architecture
Fall 2008 ©
Digital Systems
Digital vs. Analog Waveforms
+5
+5
1
0
1
V
V
Time
T ime
–5
–5
Digital:
only assumes discrete values
Analog:
values vary over a range continuously
Computer Architecture
Fall 2008 ©
Digital Hardware Systems
Boolean Algebra and Logical Operators
Algebra: variables, values, operations
In Boolean algebra, the values are the symbols 0 and 1
If a logic statement is false, it has value 0
If a logic statement is true, it has value 1
Operations: AND, OR, NOT
X
Y
X AND Y
X
Y
X OR Y
X
NOT X
0
0
1
1
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
0
Computer Architecture
Fall 2008 ©
Example: Seven Segment Display
°Chip to drive digital display
L1
L
4
L
6
L2
L
5
L
7
L3
B3
0
0
0
0
0
0
0
0
1
1
Computer Architecture
B2
0
0
0
0
1
1
1
1
0
0
B1
0
0
1
1
0
0
1
1
0
0
B0
0
1
0
1
0
1
0
1
0
1
Val
0
1
2
3
4
5
6
7
8
9
Fall 2008 ©
Example (cont.)
L1
L
4
L
6
L2
L
5
L
7
L3
B3
B2
B1
B0
Val
L1
L2
L3
L4
L5
L6
L7
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
0
2
1
1
1
0
1
1
0
0
0
1
1
3
1
1
1
0
0
1
1
0
1
0
0
4
0
1
0
1
0
1
1
0
1
0
1
5
1
1
1
1
0
0
1
0
1
1
0
6
1
1
1
1
1
0
1
0
1
1
1
7
1
0
0
0
0
1
1
1
0
0
0
8
1
1
1
1
1
1
1
1
0
0
1
9
1
1
1
1
0
1
1
Computer Architecture
Fall 2008 ©
Example (cont.)
°Implement L4:
B3
B2 B1 B0 L4
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
Some gate level implementation
of the Boolean function for L4
Computer Architecture
Fall 2008 ©
Representations of Digital Design: Switches
A switch connects two points under control signal.
Normally Open
when the control signal is 0 (false), the switch is open
when it is 1 (true), the switch is closed
Normally Closed
when control is 1 (true), switch is open
when control is 0 (false), switch is closed
True
Cont rol
True
Clos ed
Sw it ch
Cont rol
False
Normally Open
Sw it ch
Open
Sw it ch
False
Normally Clos ed
Sw it ch
Open
Sw it ch
Clos ed
Sw it ch
Computer Architecture
Fall 2008 ©
Switch Representations
Examples:
routing inputs to outputs through a maze
EXAMPLE:
IF car in garage
AND garage door open
AND car running
THEN back out car
Car in
garage
Car
running
Car can
back out
True
EXAMPLE:
IF car in driveway
OR (car in garage
AND NOT garage door
closed)
AND car running
THEN can back out car
Garage
door open
Garage door
closed
Car in
garage
True
Car
running
Car can
back out
True
Car in
driveway
Floating nodes:
what happens if the car is not running?
outputs are floating rather than forced to be false
Under all possible control signal settings
(1) all outputs must be connected to some input through a path
(2) no output is connected to more than one input through any path
Computer Architecture
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Steering Logic: Switches
Voltage Controlled Switches
Gate
Channel
Region
Oxide
Source
Drain
Silicon Bulk
n-type Si
p-type Si
"n-Channel MOS"
Metal Gate, Oxide, Silicon Sandwich
Diffusion regions: negatively charged ions driven into Si surface
Si Bulk: positively charged ions
By "pulling" electrons to the surface, a conducting channel is formed
Computer Architecture
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Switching or Steering Logic
Voltage Controlled Switches
Gate
Source
Drain
Logic 1 on gate,
Source and Drain connected
nMOS Transistor
Gate
Source
Logic 0 on gate,
Source and Drain connected
Drain
pMOS Transistor
Computer Architecture
Fall 2008 ©
Using Switches to implement Logic
Inverter Operation
+5V
"1"
+5V
"0"
"0"
Input is 1
Pull-up does not conduct
Pull-down conducts
Output connected to GND
"1"
Input is 0
Pull-up conducts
Pull-down does not conduct
Output connected to VDD
Computer Architecture
Fall 2008 ©
NAND Gate
NAND Gate Operation
"1"
"0"
"1"
+5V
"1"
+5V
"0"
A = 1, B = 1
Pull-up network does not conduct
Pull-down network conducts
Output node connected to GND
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"1"
A = 0, B = 1
Pull-up network has path to VDD
Pull-down network path broken
Output node connected to VDD
Fall 2008 ©
NOR Gate
NOR Gate Operation
"0"
"1"
"0"
+5V
"0"
+5V
"1"
A = 0, B = 0
Pull-up network conducts
Pull-down network broken
Output node at VDD
"0"
A = 1, B = 0
Pull-up network broken
Pull-down network conducts
Output node at GND
Computer Architecture
Fall 2008 ©
Switch Representations
Implementation of AND and OR Functions with Switches
A
False
B
A
output
True
AND function
Series connection to TRUE
False
B
output
True
OR function
Parallel connection to TRUE
Computer Architecture
Fall 2008 ©
Representations of a Digital Design
Truth Tables
tabulate all possible input combinations and their associated
output values
Example: half adder
adds two binary digits
to form Sum and Carry
A
0
0
1
1
B
0
1
0
1
Sum
0
1
1
0
Example: full adder
adds two binary digits and
Carry in to form Sum and
Carry Out
Carry
0
0
0
1
A
0
0
0
0
1
1
1
1
NOTE: 1 plus 1 is 0 with a
carry of 1 in binary
Computer Architecture
B Cin
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Sum Cout
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
Fall 2008 ©
Representing Digital Design: Boolean Algebra
values: 0, 1
variables: A, B, C, . . ., X, Y, Z
operations: NOT, AND, OR, . . .
NOT X is written as X
X AND Y is written as X & Y, or sometimes X Y
X OR Y is written as X + Y
Deriving Boolean equations from truth tables:
A B
0
0
1
1
0
1
0
1
Sum Carry
0
1
1
0
Sum = A B + A B
OR'd together product terms
for each truth table
row where the function is 1
0
0
0
1
if input variable is 0, it appears in
complemented form;
if 1, it appears uncomplemented
Carry = A B
Computer Architecture
Fall 2008 ©
Representing Digital Logic: Boolean Algebra
Another example:
A
B
Cin
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sum Cout
0
1
1
0
1
0
0
1
Sum = A B Cin + A B Cin + A B Cin + A B Cin
0
0
0
1
0
1
1
1
Cout = A B Cin + A B Cin + A B Cin + A B Cin
Computer Architecture
Fall 2008 ©
Gate Representations of a Digital Design
most widely used primitive building block in digital system design
Standard
Logic Gate
Representation
Half Adder Schematic
A
Inverter
SUM
AND
B
OR
CARR Y
Net: electrically connected collection of wires
Netlist: tabulation of gate inputs & outputs
and the nets they are connected to
Computer Architecture
Fall 2008 ©
Representations of a Digital Design: Gates
Full Adder Schematic
\Cin \ B \ A
Cin B
A
A
B
SUM
Cin
A
B
Cout
B
Cin
Cout
A
Cin
Fan-in: number of inputs to a gate
Fan-out: number of gate inputs an output is connected to
Technology "Rules of Composition" place limits on fan-in/fan-out
Computer Architecture
Fall 2008 ©
Waveform Representation
dynamic behavior of a circuit
real circuits have non-zero delays
Timing Diagram of the Half Adder
100
200
A
B
SUM
CARRY
sum
sum
propagation
propagation
delay
delay
circuit hazard: 1 plus 0 is 1, not 0!
Output changes are delayed from input changes
The propagation delay is sensitive to paths in the circuit
Outputs may temporarily change from the correct value to the
wrong value back again to the correct value: this is called
a glitch or hazard
Computer Architecture
Fall 2008 ©
Routing Stuff Around – Multiplexors and Demultiplexors
Multi-point connections
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Multiple input sources
Sb
Sum
Ss
Multiple output destinations
DEMUX
S0
S1
Computer Architecture
Fall 2008 ©
So far Combinatorial (or stateless) logic
°Things don’t get really interesting until we
have memory elements
• Think about a digital watch, or a vending
machine (or a microprocessor!)
• This is called “Sequential Logic”
°Two questions:
• How do we design memory elements?
- How do we create logic that remembers?
• How do we design sequential logic
Computer Architecture
Fall 2008 ©
Memory Elements
°The trick is to use feedback
"1"
Cascaded Inverters: Static Memory Cell
"0"
D
Q
Clk
°Example: D-Latch
D
Clk
°Latch vs. Flip Flop
Q
• Flip flop: two latches in a row
• Allows you to read the old value and write a
new value without a race condition
Computer Architecture
Fall 2008 ©
Sequential Logic Design
inputs
outputs
Combinatorial
Logic
Current state
Next state
State
° State as part of the input
° Next state as part of the output
° State stored in flip flops (registers!)
° Clock controls everything (synchronous logic)
° Lets rethink our 8 segment display example to make it
display a counter
Computer Architecture
Fall 2008 ©
Take home points
°Logic built using switches (transistors)
°Boolean algebra and truth tables
°Translation to gates: sum of products
°Multiplexors, demultiplexors, ALU … all
designed this way
°Sequential logic
• Memory elements
• Old state part of inputs, next state part of
outputs
• Counters, registers, control all designed this
way
Computer Architecture
Fall 2008 ©