Download Intro. Digital System Design

Digital System Design and Labs
數位系統與實驗
歐陽明(Ming Ouhyoung)
Professor, Dept.of CSIE,
National Taiwan University
課名: 數位系統與實驗 課號: CSIE 2344 班次: 1, 必修 授課:
歐陽明
英文課名:Digital System Design and Lab
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大綱:
Digital System Labs
Introduction to Boolean Algebra and Digital System Design
The Process of Design, Rapid Electronic System Prototyping
Minimization of Boolean Function
Combinational Circuits
Programmable and Steering Logic
Sequential Logic Design (Reverse Engineering and Forward Design)
Finite State Machine Design, Hardware Description Languages
Digital System Labs: Case Study (ALU design, Memory Control etc.)
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• 教科書
Contemporary Logic Design, Second Edition, Randy Katz, Gaetano Borriello
• Prentice Hall, 台北圖書代理 Paperback, US40
Where is this course in the CSIE
course map?
(1) Circuits and Micro-Electronics (optional)
THEN
(2) Digital System Design and Laboratory
THEN
(3) Computer Architecture, or
(4) VLSI design, or (5) Embedded System Design
Digital vs. Analog Systems
• Difference
• How to bridge these two systems?
AD and DA converter
Expected capabilities for students
(see the demos!)
(1)Understand the Digital System Design
principles
(2) Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)
(3) Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)
Hardware Description Languages
1. VHDL (demo)
2. Verilog (demo)
VHDL
• VHDL was originally developed at the request
of the U.S Department of Defense in order to
document the behavior of the ASICs that
supplier companies were including in
equipment.
VHDL
• The idea of being able to simulate the ASICs
from the information in this documentation
was so obviously attractive that logic
simulators were developed that could read
the VHDL files. The next step was the
development of logic synthesis tools that read
the VHDL, and output a definition of the
physical implementation of the circuit.
logic synthesis
In electronics, logic synthesis is a process by
which an abstract form of desired circuit
behavior, is turned into a design implementation
in terms of logic gates. Common examples of
this process include synthesis of HDLs,
including VHDL and Verilog. Some tools can
generate bitstreams for
programmable logic devices such
as PALs or FPGAs, while others target the
creation of ASICs. Logic synthesis is one aspect
of electronic design automation.
Combinational logic vs. Sequential
logic (with registers)
• A synchronous circuit consists of two kinds of
elements: registers and combinational logic.
Registers (usually implemented as D flip-flops)
synchronize the circuit's operation to the
edges of the clock signal, and are the only
elements in the circuit that have memory
properties. Combinational logic performs all
the logical functions in the circuit and it
typically consists of logic gates.
Combinational logic and Sequential
logic (example)
Reverse Engineering
Can write a program for Reverse Engineering
(Read a circuit from the System Design, and
explain its function, by a program)
Results (a finite state machine!)
Mealy machine vs Moore machine
• In the theory of computation, a Moore
machine is a finite-state machine whose
output values are determined solely by its
current state.
• In the theory of computation, a Mealy
machine is a finite-state machine whose
output values are determined both by its
current state and the current inputs.
Can write a program for Forward Design
(Read a finite automata or finite state machine,
then generate the circuits with logic gates)
Example: design a counter that can count from
1 to 5 (and input bits can overlap).
Results (a logic circuit design)
Two types of results of circuit Implementation
• (1) 電路板 (麵包板, breadboard) or FPGA (fieldprogrammable gate array)
Results of Implementation (II)
(可送台積電, 聯電製造)
(2) A chip (ASIC, application specific integrated
circuits)
That’s why you need the logic lab
in Dept. of CSIE!
To do the FPGA implementation with
breadboard, or chip deign
By writing programs (VHDL, Verilog etc.)!
(and you need debugging, also in hardware, to
be sure that your product is correct!)
THEN you need: logic analyzer (邏輯分析儀,
4GHz one, for example),
logic analyzer
• a laboratory test instrument designed to
display and evaluate digital signals. The device
works in a manner similar to the way that
an oscilloscope displays and facilitates the
analysis of analog signals.
• A logic analyzer allows engineers to design,
optimize, and debug the hardware in digital
systems, and can help technicians find and fix
problems in malfunctioning systems.
What is the cost of a product from
design to implementation?
(for a machine/a circuit)
• In terms of total time and money used
Design goals: constraints=
Design fees + manufacture+ support
Total Cost of Circuit/Chip Design
• Cd: design cost, shared by all products N
• Cm: manufacture cost
• Cs: field support cost, including relibility of
components, interconnection, servicing cost
• Solution: Early prototyping, Design for
testability, Programmability (like software
design, using VHDL, Verilog etc IEEE standards)
From design to implementation
to debug
Design considerations/constraints
Dynamic changes of hardware design
Radical change in logic design (Chap. 1.1)
(1) Automatic generation of logic circuits using
software tools.
(2) Versatile digital components (programmable,
FPGA, PLA--programmable logic array etc.)
(3) Design emphasis: shifting from detailed
implementation hardware to the software
specification.
Problems: software design, face same problems
in writing a program!
The elements of modern design
Representation, circuit technology,
rapid prototyping
Digital hardware systems
The art of design:
to design is to represent
Semiconductor theory:
Why TSMC needs neno tech.?
• (1) Can you explain the function of the
following CMOS inverter, in terms of
Vin (gate voltage), and how the CMOS will
work in terms of fundamental semi-conductor
theory (electron or hole flow)? What is the
cause of flow of electrons or holes?
Neno(meter) technology
• 1 Angstrom = 10 to the -10 meters
• 1 Neno-meter = 10 to the -9 meters,
so, 1 nenometer is equivalent to 10
Hydrogen atoms
TSMC : industry leading 20/28 nm (Q4 2015, 16
nm) semiconductor process technology
Collaborates with Fujitsu on 28 nm process
CMOS inverter physical layers
Semi-conductor theory II
(2) When the poly-silicon and diffusion layer
width is reduced by a factor of R, so are others.
Please answer what is the packing density
(gates/area)? power/gate, gate delay (speed) in
terms of R. Explain with simple explanations
using the following models, and make your own
assumptions.
Scaling assumptions
**Voltage scaled by R, oxide thickness (T0) scaled by R,
then device current is scaled by R,
Depletion region width scaled by R, increase the
substrate doping, NA, by R
To simplify the condition:
• Case 1: The source-drain voltage, the width, the length, the
source-drain current flow, and the oxide thickness are ALL
reduced by R.
CMOS inverter physical layers
Circuit theory
• Delay T is proportional to
Capacitor C and Impedance (Resistance) R
delay T = R*C
speed S is inversely proportional to T
R is proportional to length(L), and inversely
proportional to width(W) of resistor: L/W
C is proportional to area (A) divided by distance
(D)of two plates:
A/D
Basic scaling properties
• Parameter
Dimension L
W
t0 (Oxide thickness)
scaling factor
1/R
1/R
1/R
Doping concentration
R
Voltage
1/R
Current
1/R
(current is proportional to W/L*V2/t0 )
The effect of scaling (k)
Packing density
Capacitance
R2
1/R
Power/gate (VI)
Chip power density
Gate delay, (CV/I)
Power/delay product
1/R2
1
1/R
1/R3
Intro. VLSI: Carver Mead (Caltech)Lynn Conway (Xerox
Parc) 1980
CMOS inverter
CMOS inverter: black and white
representation
Transistors in row
Symmetrical arrangement of
transistors (FETs)
Basic design rule checking
Design rule checking
Some example of DRC's in IC design
include:
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Active to active spacing
Well to well spacing
Minimum channel length of the transistor
Minimum metal width
Metal to metal spacing
Metal fill density (for processes using CMP)
ESD and I/O rules
Antenna effect
Rules for design rule checking:
basic rules
Four bit counter: with flip-flops
Toggle cell stick diagram
A counter layout
Gate array for four-input CMOS
NOR gates
PLA layout
Reverse engineering: guess what is
this?
Expected capabilities after this
course
• (1) Design (forward design)
• (2) Analysis (reverse engineering)
see the exam problem sets.
(3) Get to know how to build a chip or
computer, and the working environment of
chip/computer design companies.
(4) The world trend in hardware and
software integration.