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UNIT WISE MCQ
Unit-I
1. The time takes for the output of a logic circuit to change from one state another state is called [
]
A) Rise time
B) Fall time
C) Propagation time
D) Transition time
2. Dynamic characteristics of CMOS mainly depend on
[
]
A) Capacitive load B) Resistive load
C) Both A&B
D) None
3. First integrated circuit logic family was introduced in
[
]
A) 1960
B) 1947
C) 1820
D) 1957
4. The inverter 74AL S04 has the following specifications
(Gate-97)
[
]
IOH max = -0.4mA, IOL max = 8mA , IIH max = 20µA ,IIL max = -0.1mA the fan out based on above will be
A) 10
B) 20
C) 60
D) 100
5. Transistor can act as a switch in which region
[
]
A) Cut off region
B) Saturation region C) Active region
D) All the above
6. Sink current makes the output is at which state
[
]
A) Low
B) High
C) Undefined
D) None
7. A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate
in order to
(Gate-99)
[
]
A) In increase its IOL
B) Reduce its IOH
C) Increase its speed of operation
D) Reduce power dissipation
8. Which logic family is the fastest logic family
[
]
A) PMOS
B) NMOS
C) CMOS
D) ECL
9. TTL output stage is called
[
]
A) Totem pole
B) Pushback
C) Pullback
D) Pull down
10. Logic family that dissipates more power
[
]
A) TTL
B) ECL
C) CMOS
D) DTL
11. The power consumption of a CMOS in DC condition is known as
[
]
A) Static
B) Quiescent
C) A or B
D) None
12. Interfacing of different logic families what type of parameters are considered
[
]
A) Fan out
B) Load capacitance C) Noise margin
D) All the above
13. Source current makes output logic is at which state
[
]
A) Low
B) High
C) Undefined
D) None
14. Which Regions of transistor acts as OFF and ON switch respectively
[
]
A) Active& saturation region
B) Cutoff region &saturation
C) Cutoff & active region
D) All the above
15. The noise margin of a TTL gate is about
(Gate-98)
[
]
A) 0.2V
B) 0.4V
C) 0.6V
D) 0.8V
16. Commercially available ECL gates use two ground lines and one negative supply in order to
(Gate-99)
[
]
A) To reduce power dissipation
B) Increase fan-out
C) Reduce loading effect
D) Eliminate the effect of power line glitches or the biasing circuit
17. For the difference between Voh (min)-Vih (min) and Vil (max)-Vol (max) differences should be [
]
A) Positive value
B) Negative value
C) Zero
D) Any value
18. Which logic family has high input impedance
[
]
A) TTL
B) CMOS
C) ECL
D) RTL
19. In standard TTL the totem pole stage refers to
(Gate-97)
[
]
A) The multi emitter input stage
B) The phase splitter
C) The output buffer
20. Sink current indicates the output of CMOS as
A) Logic 0
B) Logic 1
21. State ‘0’ representing bit in TTL logic is
A) 0-1.5V
B) 3.5-5V
22. In PMOS transistor Vgs is increased then Rds is
A) Increases
B) Decreases
23. Power dissipation of CMOS in DC will be
A) High
B) Low
24. High state noise margin is defined as
A)Vnh=Vil (max)-Voh (min)
D) Open collector output stage
C) Both A&B
C) 0-0.8V
C) Remains constant
C) Very low
[
D) All the above
[
D) 2.0-5.0V
]
]
[
]
[
]
[
]
D) None
D) Very high
B) Vnh=Vil (max)-Vol(max)
C)Vnh=Voh (min) -Vih (min)
D) Vnh=Vol(max)-Vil(max)
25. A diode can act as a switch in which bias
[
A) Reverse
B) Forward
C) Zero
D) None
26. Fan-out defined as
[
A) No of gates it can drive B) No of gates it can driven
C) Both
D) None
27. Which logic family consumes less power
[
A) CMOS
B) TTL
C) ECL
D) DTL
28. The output of the 74 series of TTL gates is taken from a BJT in
(Gate-03)
[
A) Totem pole and common collector configuration
B) Either totem pole or common collector configuration
C) Common base configuration
D) Common collector configuration
29. NMOS transistor has
[
A) Low mobility & high resistance
B) High mobility & low resistance
C) Low mobility & low resistance
D) High mobility & high resistance
30. Dynamic characteristics of CMOS is mainly depends on
[
A) Capacitive load B) resistive load
C) Both A&B
D) None
31. Source current indicates the output voltage of CMOS as
[
A) 1
B) 0
C) Both A&B
D) All the above
32. The full forms of the abbreviations TTL and CMOS in reference to logic families are (Gate-09)[
A) Triple transistor logic and chip metal oxide semiconductor
B) Tri state transistor logic and chip metal oxide semiconductor
C) Transistor transistor logic and complementary metal oxide semiconductor
D) Tri state transistor logic and complementary metal oxide silicon
33. ON resistance of PMOS is
[
A) Less
B) HIGH
C) Zero
D) None
34. The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
(Gate-97)
[
A) The driver transistor has a larger threshold voltage than the load transistor
B) The driver transistor has a larger leakage currents compared to the transistor
C) The load transistor has a smaller W/I ratio compared to the driver transistor
D) None of the above
35. Which is an act as a voltage controlled resistance?
[
A) TTL
B) DTL
C) RTL
D) MOS
]
]
]
]
]
]
]
]
]
]
]
36. To make a Schottky transistor the schottky diode is placed in between which terminals
[
]
A) Emitter and base B) Collector and base C) Emitter and collector D) None
37. In HC logic levels VOHmin is
[
]
A) 1.5V
B) 3.5V
C) 3.84V
D) 0.33V
38. TTL output stage is called
[
]
A) Totem pole
B) Pushback
C) Pullback
D) Pull down
39. HCMOS stands for
[
]
A) Highest CMOS
B) High level CMOS C) High Speed CMOS
D) High State CMOS
40. Among the digital IC-families ECL, TTL and CMOS
(Gate-89)
[
]
A) ECL has least propagation delay
B) TTL has the least Fan-out
C) CMOS has the biggest noise margin
D) TTL has the low power consumption
2 MARKS QUESTIONS
UNIT-I
1. State CMOS logic levels?
2. Define Fan-in, Fan-out?
3. What is a logic family?
4. Draw the symbol of NMOS and PMOS transistor?
5. What is sink current and Source current?
6. Write short note on transition time?
7. Define propagation delay?
8. What are the different CMOS logic families?
9. Write short note on transistor logic inverter?
10. Define TTL logic levels and noise margin?
11. Draw the circuit diagram of ECL inverter?
12. Write short note on ECL voltage levels?
13. What is schottky transistor?
14. Compare any four parameters of TTL, CMOS and ECL?
15. Define static and dynamic power dissipation?
16. Draw the logic diagram of CMOS AND-OR-INVERT gate?
17. What do you mean by current spikes?
18. State the effects of loading CMOS output?
19. Draw the circuit diagram of 2 input NAND gate?
20. What do you mean by 5V tolerant output?
10 MARKS QUESTIONS
UNIT-1
1) a) Design a 4-input CMOS AND-OR-INVERTER gate .draw the logic diagram and functional table?
b) Draw the resistive model of a CMOS inverter and explain its behavior for LOW and HIGH outputs?
2) Draw the circuit diagram of basic CMS gate and explain the operation?
b) Compare CMOS, TTL and ECL logic families.
3) a) Draw the circuit diagram of a two input LS-TTL nor gate and explain the functional behavior?
b) Explain in detail about basic ECL logic circuit. (L2)
4) Design the ECL 10K OR/NOR gate and explain its functionality?
5) a) Design CMOS transistor circuit for 2-input AND gate. With the help of function table explain the circuit.
b) Design a CMOS circuit that has the functional behavior f(Z)=A.(B+C).
6) a) What is the difference between transition time and propagation delay? Explain these two parameters with
reference to CMOS logic.
b) Explain sinking current and sourcing current of TTL Output. Which of the above parameters decide the fan
out and how?
7) a) Distinguish between static and dynamic power dissipation of CMOS circuit. Derive the expression
for dynamic power dissipation.
b) Compare HC, HCT, VHC and VHCT CMOS logic families.
8) a) Design a three input NAND gate using diode logic and a transistor inverter. Analyze the circuit with the help
of transfer characteristics.
b) Explain the following terms with reference to TTL gate.
i) D.C noise margin ii) Logic levels
9) a) Draw the circuit diagram of basic TTL NOR gate and explain the three parts with the help of functional
operation.
b) Explain TTL and CMOS interfacing.
10) a. State CMOS logic levels.
b. Define Fan-in, Fan-out.
c. Draw the symbol of NMOS and PMOS transistor.
d. Define TTL logic levels and noise margin.
e. Define static and dynamic power dissipation.
Unit-II
1. Component declaration comes under what type of modeling
[
]
A) Structural
B) Behavioral
C) Data flow
D) All
2. Timing analysis is not considered in what type of modeling
[
]
A) Data flow
B) behavioral
C) Structural
D) All the above
3. Generate statement is similar as
[
]
A) For
B) While
C) If
D) case
4. Which one accepts a number of arguments and returns a result
[
]
A) Function
B) package
C) library
D) Both A and B
5. A function can be used in the place of a what
[
]
A) Expression
B) Statement
C) Both A and B
D) None
6. Which is a standard library at the beginning of the design
[
]
A) IEEE
B) Work
C) Both A and B
D) None
7. A Port is used in the following syntax
[
]
A) Architecture
B) Entity
C) Concurrent statements
D) Sequential statements
8. Comments start after which symbol in VHDL
[
]
A) -B) !!
C) ##
D) @@
9. Which type of models is present in VHDL
[
]
A) Data flow
B) Behavioral
C) Structural
D) All the above
10. Package contains the definitions of what
[
]
A) Procedures
B) Objects
C) Functions
D) Libraries
11. VHDL stands for
[
]
A) Hard ware description language B) very high speed IC HDL C) highest HDL D) None
12. Which one is not a HDL in the following
[
]
A) Verilog
B) ABEL
C) VHDL
13. Which one is not a mode declaration signal
A) IN
B) OUT
C) Component
14. VHDL Program structure is a combination of
A) Entity
B) architecture
C) Both
15. Which of the following is a example of Boolean operators
A) AND
B) MOD
C) ABS
16. VHDL support what type of modeling
A) Data flow
B) Structural &Behavioral C) Behavioral Only
17. In VHDL which is a detailed description of the module
A) Entity
B) Architecture
C) Both
18. “If then else” VHDL statement used within
D) PASCAL
[
]
[
]
[
]
D) Buffer
D) None
D) REM
[
D) Both A and B
[
D) Process
[
]
]
]
A) Process
B) select
C) assert
D) WHILE
19. Signals that can be defined in a package are ……….. Signals
[
]
A) Global
B) Local
C) Both
D) None
20. Simulation is a
[
]
A) Timing delay
B) functional verification
C) RTL conversion D) Net list
21. Process statements are used in what type of modeling
[
]
A) Structural
B) Behavioral
C) Data flow
D) All
22. A procedure can be used in the place of a
[
]
A) Statement
B) Object
C) Expression
D) Function
23. VHDL defines many character strings called---[
]
A) Reserved words B) Key words
C) Both A and B
D) None
24. Which signal is an output of the entity, and its value can also be read inside the entity’s architecture
[
]
A) Input
B) Output
C) Buffer
D) In out
25. Synthesis means
[
]
A) Net list
B) power dissipation amount C) Both A and B
D) None
26. The type of Integer is defined as the range of integer values including at least range
[
]
31
31
31
31
31
31
31
31
A) - 2 +1 to + 2 -1 B) +2 +1 to +2 -1
C) - 2 +1 to - 2 -1 D) + 2 +1 to -2 -1
27. VHDL specifies a time delay using the keyword
[
]
A) Loop
B) While
C) After
D) All
28. VHDL describe a circuit in terms of flow of data operations on it within the circuit is called [
]
A) Structural
B) Behavioral
C) Data flow
D) All
29. Simulator operator begins at simulation time of
[
]
A) Zero
B) One
C) Two
D) Three
30. Begin is used in the following syntax
[
]
A) Architecture
B) Entity
C) Concurrent statements
D) Sequential statements
31. A VHDL -----accepts number of arguments and a returns a result.
[
]
A) Function
B) Variables
C) Packages
D) None
32 .Which type of port declaration used in VHDL
[
]
A) Module
B)Simulation
C) Entity
D) Architecture
32. A VHDL ------- is a place where the VHDL compiler stores information about a particular design project
[
]
A) Package
B) Function
C) Variable
D) Library
33. Which types of models are present in VHDL
[
]
A) Data flow
B) Behavioral
C) Structural
D) All the above
34 .Process statements are used in ………..design low
[
]
A) Data flow
B) Behavioral
C) Structural
D) All the above
35 .Generic declarations is used in which design flow
[
]
A) Data flow
B) Behavioral
C) Structural
D) All the above
36. Which of the following is the fastest adder
[
]
A) Half adder
B) Full adder
C) Carry look ahead adder D) Ripple carry adder
37. In which module inputs & outputs are declared
[
]
A) Entity
B) Architecture
C) Instantiate
D) None
38. Which one is to describe the detailed description of the module’s internal behavior
[
]
A) Entity
B) Signal
C) Architecture
D) None
39. The reserved words are
[
]
A) Entity
B) Port
C) Is
D) all the above
40. Buffer is what type of mode
[
]
A) Input
B) Output
C) Signal
D) None
2 MARKS QUESTIONS
UNIT-II
1. What is HDL?
2. Write Syntax of entity declaration?
3. Write short note on Simulation?
4. Write an example of structural design elements?
5. Write short note on behavioral design elements?
6. Write syntax of process statement in VHDL?
7. Define time dimension?
8. Define functional simulation and timing simulation?
9. What do you mean by Signal in VHDL?
10. What are the different steps of HDL design flow?
11. What is entity and architecture declaration in VHDL program structure?
12. What are the different keywords in VHDL program?
13. Define types and constants?
14. Define library and library clause?
15. Write the Syntax of package?
16. What do you mean by Concurrent Statements?
17. Give the features of VHDL?
18. Write short note on Synthesis?
19. What is different modeling Styles of VHDL?
20. What are different data types of VHDL?
10 MARKS QUESTIONS
UNIT-II
Explain the various data types supported by VHDL. Give the necessary examples.
(b) Explain about VHDL program structure.
2) a) Explain about functions and procedures with an examples.
b) Explain about libraries and packages.
3) a) Design a logic circuit to detect prime number. Write the VHDL program for it.
b) Design the logic circuit and write a data-flow style VHDL program for the following function.
F (P) = ∑A,B,C,D (1,5,6,7,9,13) + d(4,15).
4) Draw and explain in detail of VHDL design flow.
5) a) Write about structural design elements with VHDL code.
b) Write a VHDL entity and Architecture for the following function. F(x) = (a + b) (c d) Also draw the relevant
logic diagram.
6) Design the logic circuit and write VHDL program for the following functions.
a) F(X) = ∑A, B, C, D (0, 2, 5, 7, 8, 10, 13, 15) + d (1, 6, 11).
b) F(Y) = ∏A, B,C,D (1, 4, 5, 7, 9, 11, 12, 13, 15).
7) Design a logic circuit to detect prime numbers and write the VHDL code with component declaration
8. Explain in detail different modeling styles of VHDL with suitable examples.
9) a) What is the importance of time dimension in VHDL and explain.
b) Explain the behavioral design elements of VHDL.
10. Write Short notes
a) Syntax of entity declaration.
b) Process statement in VHDL.
c) Difference between Signal and Variable.
d) Difference between Function and Procedure.
e) IEEE Library.
Unit-III
1. One of the following is a 3 to 8 decoder
[
]
A) 74LS139
B) 74X138
C) 74X129
D) 74X119
2. 74 X 148 outputs are
[
]
A) Active low
B) Active high
C) Buffered
D) Inverted
3. Which one is the octal three state Trans receiver IC
[
]
A) 74 X 245
B) 74 X 254
C) 74 X 243
D) 74 X 241
4. What is the IC number of 4bit binary adder
[
]
A) 74 X 283
B) 74 X 263
C) 74 X 143
D) 74 X 148
5. In VHDL ‘V’ stands for
[
]
A) VHSIC
B) VIC
C) VHS
D) Verilog
6. A seven segment decoder has the input code is
[
]
A) 4 bit BCD
B) 6 bit excess 3
C) 3 bit octal
D) 3 bit hex
7.32X1multiplexer implemented by using
[
]
A) 74 X 139, four 74 X 151
B) 74 X 136, two 74 X 151
C) 74 X 131, four 74 X 155
D) 74 X 130, four 74 X 159
8. Which of the following IC specifies the comparator
[
]
A) 74 X 245
B) 74 X 541
C) 74 X 85
D) 74 X 148
9. A 2 bit binary multiplier can be implemented using
(Gate-97)
[
]
A) 2 input AND gates only
B) 2 input XOR and 4-inputs AND gates only
C) Two 2 input NORs and one XNOR gate
D) XOR gates and shift registers
10. Which of the following IC specifies the Full-adder
[
]
A) 74 X 999
B) 74 X 99
C) 74 X 199
D) 74 X 289
11. How many 2 to 4 decoders with enable input are needed to construct a 4 to 16 decoder
[
]
A) 4
B) 5
C) 6
D) 8
12. Decimal 43 in hexadecimal and BCD number system is
[
]
A) B2, 01000011
B)2B, 01000011
C) 2B, 00110100
D) B2,00110100
13. The minimum number of NOR gates required to implement XNOR gate is
[
]
A) 4
B) 5
C) 6
D) 7
1 1
1
1
1
1
1
14. In the logic equation A (A+B C +C)+B (C +A +BC)(A+B C+AC )=1 if C=A1 then
[
]
1
1
A) A+B
B) A +B
C) A+B
D) A=1
15. Which of the following IC is 8 input priority encoder
[
]
A) 74x283
B) 74X151
C) 74X182
D) 74x148
16. One of the following is 3 to 8 decoder
[
]
A) 74X130
B) 74X119
C) 74X36
D) 74X138
17. 2 to 4 decoder is
[
]
A) 74X139
B) 74X130
C) 74X129
D) 74X119
18. Which is have 4inputs, 2 bit multiplexer
[
]
A) 74 × 541
B) 74 × 148
C) 74 × 153
D) 74 × 151
19. The VHDL code for difference bit in full sub tractor is
[
]
A) Diff <= x XOR Y XOR bin;
B) diff <= x NAND Y OR bin;
C) Diff <= x XNORY XOR bin;
D) diff <= x XNORY OR bin;
20. One of the following is OR gate
[
]
A) 74X20
B) 74X119
C) 74X36
D) 74X138
21. For 1X32 DEMUX necessary select lines are
[
]
A) FIVE
B) FOUR
C) THREE
D) EIGHT
22. Memory element is consists in which circuitry
[
]
A) Combinational logic B) Sequential logic
C) Both
D) None
23. N No. of inputs and 2N No. of outputs logic circuit is
[
]
A) Decoder
B) Encoder
C) Multiplexer
D) Demultiplexer
24. Memory present in which circuits
[
]
A) Combinational
B) Sequential
C) Both
D) None
25. Which one acts a digital switch
[
]
A) Multiplexer
B) Demultiplexer
C) Buffer
D) Encoder
26. Without any additional circuitry, an 8:1 mux can be used to obtain
(Gate-03)
[
]
A) Some but not all Boolean functions of 3 variables
B) All functions of 3 variables but none of 4 variables
C) All functions of 3 variables and some but not all of 4 variables
D) None
27. The most basic 3 state device is a
[
]
A) Buffer
B) Enable
C) Identifier
D) Fitter
28. Design of full adder how many no of half adder all require
[
]
A) 2
B) 3
C) 4
D) 5
29. The output Y of a 2-bit comparator is logic 1 whenever the 2 bit input A is greater than the 2-bit input B.
The no. of͞͞ combinations for which the output logic 1 is
(Gate-12)
[
]
A) 4
B) 6
C) 8
D) 10
30. In a half-sub tractor circuit with X and Y as inputs, the borrow (M) and difference (N=X-Y)
are given by
(Gate-14)
[
]
A) M= X xor Y, N=XY
B) M= XY, N= X xor Y
C) M= ͞͞XY, N= X xor Y
D) M=͞͞XY, N=͞͞͞͞X͞͞ xo͞͞r ͞͞Y
31. In Ex-OR gate when A=1 and B=0 the output is
[
]
A) 1
B) 0
C) 0 or 1
D) none
32. IC 74* 151 is an
[
]
A) 8*1 multiplexer B) 4*1 multiplexer
C) 3*1 multiplexer D) 2*1 multiplexer
33. By adding 3 to binary number the resultant code is
[
A) excess-3 code
B) gray code
C) BCD code
D) binary code
34. Output of sub tractor
[
A)Sum, Carry
B) Borrow, Difference
C) Carry, Difference D) none
35. What is IC 74182
[
A) Priority
B) Carry look ahead
C) Full adder
D) All the above
36. The logical expression of half adder sum is
[
A) A EX-OR B
B) A+B
C) AB
D) NOT AB
37. IC 7485 is a
[
A) 4 bit comparator B) 16 bit comparator
C) 8 bit comparator D) 2 bit comparator
38. What are the minimum number of 2 to 1 multiplexer required to generate a 2 input
AND gate and a 2 input EX-OR gate?
(Gate-09)
[
A) 1 and 2
B) 1 and 3
C)1 and 1
D)2 and 2
39. The minimum number of 2 to 1 multiplexer required to realize a 4 to 1 multiplexer is
(Gate-04)
[
A) 1
B) 2
C)3
D)4
40. For a binary half-subtractor having two inputs A and B , the correct set of logical expressions
For the outputs D= (A minus B) and X = barrow are
(Gate-99)
[
A) D=AB +͞͞AB , X=͞͞AB
B)D=͞͞AB +A͞͞B+A͞͞ ͞͞B
C) D=͞͞AB+A ͞͞ X=͞͞AB
D)D=AB+͞͞A͞͞ ͞͞B , X=A ͞͞B
UNIT-III
1. Define Combinational logic circuit?
2. What is Decoder?
3. Draw the circuit for 2-to-4 line decoder?
4. What is the IC number of 3-to-8 line decoder and dual 2-to-4 line decoder?
5. What are different types of encoders?
6. What is priority encoder?
7. What are 3 states in 3 state devices?
8. What is multiplexer and draw the block diagram?
9. Design 1:8 demultiplexer using two 1:4 demultiplexers?
10. What is Gray code?
11. What is Ecess-3 code?
12. Write short note on EX-OR gates?
13. What is parity bit?
14. Define parity generator and checker?
15. Draw the diagram of n-bit comparator?
16. What is Half-adder?
17. Write the features of Arithmetic logic unit?
18. Multiply 011 by 110 using binary multiplication methods?
19. Write short note on Full subtractor?
20. Draw the circuit for Full adder using two half adders?
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10 MARKS QUESTIONS
UNIT-III
1. a) Design a 4 to 16 decoder with 74×138 IC’s.
b) Write a VHDL program for the above design.
2. a) Design a Full adder and Half adder logic circuit.
b) Write VHDL code for the above design.
3. Write a process based VHDL program for the prime-number detector of 4-bit input and explain the flow using
logic circuit.
4. Write a behavioral VHDL code for a74X280 (9 input parity checker.
5. a) With the help of logic diagram explain 74×157 multiplexer.
b) Write the data flow style VHDL program for this IC.
6. Draw the logic diagram, logic symbol of 74 x 245 octal 3-state trans-receivers and explain its operation.
7. Design a priority encoder that can handle 32 requests. Use 74×148 and required discrete gates.
Provide the truth table and explain the operation.
8. a) Write a VHDL program for a 74x181 ALU.
b) Draw the structure of a 4-bit comparator and briefly explain about it. Write a structural VHDL code for it.
9. a) Draw the logic symbol of 74 x 85, 4-bit comparator and write a VHDL code for it.
b) Design a 16-bit comparator using 74×85 Ics.
10. Write Short notes on
a) Draw the circuit for 2-to-4 line decoder.
b) Draw the circuit for Full adder using two half adders.
c) List different keywords in VHDL program.
d) Define library and library clause.
e) Define parity generator and checker.
UNIT-IV
1. Which is specifying the direction of shift, type of shift and amount of shift
[
A) Barrel shifter
B) Carry save shifter C) Sequential shifter D) Group ripple shifter
2. In a floating point encoder the relation between M, E and T is
[
ET
E
E
A) M.2
B) M.2 + T
C) M.E +T
D) M.2 + T
3. In a 16 bit barrel shifter if 4 bits are shifted at a time then the control input that is enabled is [
A) S0
B) S1
C) S2
D) S3
4.Which flip-flop is also known as transparent latch
[
A) D flip-flop
B)T flip-flop
C)JK flip-flop
D) SR flip-flop
5. Race around condition is occurred in
[
A) D flip-flop
B) T flip-flop
C) JK flip-flop
D) SR flip-flop
6. The difference between the arrival times of the clock at different devices is called
[
A) Clock delay
B) Clock skew
C) Both A&B
D) none of the above
7. Both AND plane and OR plane are programmable in
[
A) PLA
B) PAL
C) Both A&B
D) PROM
8. Which of the following IC represents 4 bit binary counter
[
A) 74x163
B) 74x373
C) 74x174
D) 74x194
9. Which of the following IC represents ALU
[
]
]
]
]
]
]
]
]
]
A) 74x199
B) 74x181
C) 74x151
D) 74x143
10. Find Odd one in the following
[
]
A) FPGA
B) ASIC
C) CPLD
D) PLD
11. What type of register would shit a complete binary number in one bit at a time and shift all the
Stored bits out one bit at a time?
[
]
A) PIPO
B) SISO
C) SIPO
D) PISO
12. A ripple counter’s speed is limited by the propagation delay of
[
]
A) Each flip-flop
B) all flip-flop and gates C) only flip-flop only with gates D) only gates
13. S - R latch characteristic equation is
[
]
*
|
*
|
| |
*
|
|
*
| |
A) Q =S+R .Q
B) Q =S +R .Q
C) Q =S +R .Q
D) Q =S+R .Q
14. The device which changes from serial data to parallel data is
[
]
A) Counter
B) Multiplexer
C) Demultiplexer
D) Flip-Flop
15. An SR latch is
(Gate-95)
[
]
A) Combinational Circuit
B) Synchronous sequential circuit
C) One bit memory element
D) One clock delay element
16. One of the following VHDL statements is used for fixed point to floating point conversion [
]
A) If B (8) =1, then M < = B (8 down to 2); E < = “100“;
B) If B (10) =1, then M < = B (10 down to 7); E < = “111“;
C) If B (9) =1, then M < = B (9 down to 0); E < = “010“;
D) If B (6) =1, then M < = B (3 down to 1); E < = “001“;
20. Race-around condition occurred when the input states are
[
]
A) J=1, K=1
B) J=0, K=1
C) J=0, K=1
D) J=0,K=0
21. How many 74X85 IC’s are required for built 12bit comparator
[
]
A) Five
B) Four
C) Three
D) Eight
22. A switch-tail ring counter is made by using a single D flip-flop. The resulting circuit is a
(Gate-95)
[
]
A) SR flip flop
B)JK flip flop
C)D flip flop
D) T flip flop
23. How many NAND gates are required for design XOR gate
[
]
A) Five
B) Four
C) Three
D) Eight
24. Synchronous counters are ---- than the ripple counters.
(Gate-94)
[
]
A) Slower
B) Faster
C) Less
D) None
25. Latches are ----- triggered circuits
[
]
A) Level
B) Edge
C) control
D) Timing
26. A 4 bit modulo 16 ripple counter uses JK flip flops. If the propagation delay of each FF is 50ns, the maximum
clock frequency that can be used is equal to
(Gate-90)
[
]
A) 20MHz
B) 10 MHz
C) 5MHz
D) 4MHz
27. Group of Flip flop are connected together to form a ------[
]
A) Register
B) Counter
C) Shift register
D) None
28. Asynchronous counters are
[
]
A) Ripple counter
B) binary counter
C) mod counter
D) shift registers
29. Group of registers called
[
]
A) Shift registers
B) counters
C) flip-flops
D) none
30. Which register is used to convert data in serial form to parallel form
[
]
A) SIPO
B) PIPO
C) PISO
D) SISO
31. All the flip flops are not clocked simultaneously
[
]
A) Synchronous counters
B) Asynchronous counters
C) Combinational circuits
D) None
32. IC 7490 is a
[
]
A) Decode binary counter
B) Shift register
C) Ring counter D) Modulo counter
33. A shift register is constructed with four D flip-flops are called
[
]
A) Buffer register
B) Counter
C) Latch
D) None
34. Johnson counter also called as
[
]
A) Twisted ring counter B) Ripple counter C) Mod counter
D) None
35. The characteristics equation of D flip flop
[
]
A) D
B) not D
C) D + 1
D) (not D)+1
37. IC 74*169 is a
[
]
A) 4 bit bi-directional syn.Counter
B) 4 bit syn. Binary counter
C) 4 bit ripple counter
D) decode counter
38. The output depends on only present state of the flip flop
[
]
A) Moore circuit
B) Mealy circuit
C) Sequential circuits D) None
39. The output depends on only present state of the flip flop
[
]
A) Universal shift registers B) Shift left register C) Shift right register D) none
40. A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gates. The combination
Circuit consists of
(Gate-03) [
]
A) One AND gate
B) One OR gate
C) One AND gate and One OR gate
D) Two AND gates
2 MARKS QUESTIONS
UNIT-IV
1. Write a program for Cascading comparator?
2. What is a Sequential circuit?
3. Differentiate sequential and Combinational circuits?
4. What is Flip-Flop?
5. Write short note on RS flip flop?
6. Write short note on Master Slave JK flip flop?
7. What is Race around Condition?
8. Write short note on T flip flop?
9. Write characteristics equation of flip flop?
10. What are applications of Flip flop?
11. What is set up time and Hold time?
12. Define propagation delay?
13. Write exaction table for D and T flip flop?
14. What is Level triggering and edge triggering?
15. What is counter and draw the block diagram?
16. Define PLA and PAL?
17. What is mealy and Moore circuits?
18. Define universal shift register?
19. What is state table and state diagram?
20. Define shift register?
10 MARKS QUESTIONS
UNIT-IV
1.Write a VHDL code for fixed point to floating point conversion.
2. What is a dual priority encoder? Explain. And write VHDL code for it.
3. Design a barrel shifter forv8-bit using three control inputs. Write a VHDL program for the same in data flow
style
4. Write a VHDL code for 8 bit comparator circuit. Using this entity write a VHDL code for 24 bit comparator.
Use the structural model for it.
5. a) Distinguish between latch and flip flop .Show the logic diagram for both. Explain the operation with the help
of function table.
b. Write a VHDL code for a D-flip flop in behavioral model.
6. a) Design a self-correcting 4 bit, 4 state ring counter.
b) Design a self-correcting 4 bit, 8 state ripple counter.
7. a. Distinguish between the synchronous and asynchronous counters
.
b. What are the impediments to synchronous design?
8. What is PLD’s? Explain in detail with help of neat sketches.
9) Explain about combinational multiplier with a neat diagram.
10) Write short notes on
(i) Clock skew.
(ii) Gating the clock.
(iii) Asynchronous inputs.
(iv) Latch and Flip-flop.
(v) Ring counter.
UNIT-V
1. RAM is
[
A) Nonvolatile memory B) Volatile memory C) Contains static information D) none
2. The size of the ROM needed to implement 8x8 combinational multiplier is
[
8
16
16
16
A) 2 x8
B) 2 x8
C) 2 x16
D) 2 x8
3. Which is used to reduce the decoder size
[
A) 2D decoding
B) 3D decoding
C) Both A&B
D) none of the above
4. Choose the correct statement(s) from the following
(Gate-92)
[
A) PROM contains a programmable AND array and a fixed OR array
B) PLA contains a fixed AND array and a programmable OR array
C) PROM contains a fixed AND array and a programmable OR array
D) PLA contains a programmable AND array and a programmable OR array.
5. Which of the following IC is 8 input priority encoder
[
A) 74x283
B) 74x151
C) 74x182
D) 74x148
6. Which of following requires refreshing?
[
A) SRAM.
B) DRAM.
C) ROM.
D) EPROM.
7. Which is used to reduce the decoder size in ROM
[
A) 2 dimensional decoding
B) 1 dimensional decoding
C) 5 dimensional decoding
D) 4 dimensional decoding
8. Which of following cannot be accessed randomly
[
]
]
]
]
]
]
]
]
A) DRAM.
B) SRAM.
C) ROM.
D) Magnetic tape
9. The information in ROM is stored
[
]
A) By the user any number of times. B) By the manufacturer during fabrication of the device.
C) By the user using ultraviolet light. D) By the user once and only once.
10. RAM provides only temporary storage as it loses all of its contents when power to the system unit is shut
off. This type of storage is referred to as what.
[
]
A) Volatile
B) Sequential
C) Direct
D) Non volatile
11. Which is Secondary storage device? Which means it keeps its data after the power is turned off.[
]
A) Volatile
B) Sequential
C) direct
D) Non volatile
12. Which is indicates how much data a particular storage medium can hold
[
]
A) Access
B) Capacity
C) Memory
D) Storage
13. The amount of time required by a storage device to retrieve data and programs is
[
]
A) Access
B) Capacity
C) Memory
D) Storage
14. A PLA can be
(Gate-94)
[
]
A) As a microprocessor
B) As a dynamic memory
C) To realize a sequential logic
D) to realize a combinational logic
15. A dynamic RAM consists of
(Gate- 94)
[
]
A) 6 transistors
B) 2 transistors and 2 capacitors
C) 1 transistor and 1 capacitor
D) 2 capacitors only
16. The minimum number of MOS transistors required to make a dynamic RAM cell is (Gate-95) [
]
A) 1
B) 2
C) 3
D) 4
17. Each cell of a static RAM contains
(Gate-95)
[
]
A) 6 MOS transistors
B) 4 MOS transistors and 2 capacitors
C) 2 MOS transistors and 4 capacitors
D) 1 MOS transistors and 1 capacitors
18. Sequential circuits contains
[
A) Memory element
B) No memory element C) Both
D) None
19. Which one is used to reduce the size
[
A) One dimensional decoding B) Two dimensional decoding C) Both A and B D) None
20. Which of the following the volatile memory
[
A) ROM
B) RAM
C) Both A&B
D) PROM
]
]
]
21. Fixed function IC’s are
[
]
A) Adders
B) ALU
C) Multiplexers
D) All the above
22. ASIC stands for ---------------------[
]
A) Application specific IC B) Application speed IC C) Applicable specific IC D) None
23. FPGA stands for -------------------A) Filed programmable gate array
B) Flexible Programmable gate array
C) Function programmable gate array
D) None
24. In PROM each bit combination of the input variable is called
[
]
A) Address
B) Word
C) PAL
D) PLA
25. Data stored in a memory by a process called
[
]
A) Writing
B) Reading
C) Coding
D) Decoding
26. RAM performs
[
]
A) Read& write operations B) Only read
C) Only write
D) None
27. EEPROM stands for -----------------A) Electrically element Programmable ROM
B) Electrically Elimination program ROM
C) Elementary Erasable PROM
D) Electrically Erasable PROM
28. In ROM timing waveforms when an address must be held stable
A) tRC
B)tAA
C)tacs
B)taa
C)tacs
B)toe
C)taa
31. SRAM stands for ----------------A) Steady state RAM
B) Segment RAM
C) Synchronous RAM
32. IC 84256 is a what type of memory chip
A) Standard SRAM
B) Standard DRAM C) Synchronous RAM
33. Data hold time in SRAM is
A)tdh
B)tcw
C)tdw
34. Operating modes of synchronous SRAMs
A) 2
B) 3
C) 4
35. Data at sequence of addresses is read or write in
A) Burst transfer mode
B) single transfer mode C) DRAM
36. In DRAM stores the data is a change on
A) Capacitor
B) Resistor
C) Diode
37. CY6116A is a
A) 2K*8 static RAM
B) 4K * 8 DRAM
C) 8K*8 SSRAM
38. RAM is ---- memory.
A) Volatile
B) Non volatile
C) Dynamic
39. In DRAM which is not used
A) Clock
B) Time
C) Address
40. Which one is faster
A) SRAM
B) DRAM
C) Synchronous SRAM
2 MARKS QUESTIONS
UNIT-V
1. What is Memory and what are different types?
2. Define ROM?
3. What is Read mode?
4. What are characteristics of ROM?
5. What is Programming mode?
6. What are the different types of ROMs?
7. What is Decoding?
8. Define tRC and tAA in ROM timing waveform?
9. Define RAM?
10. What is Static RAM?
11. Define tOE and tHZ in RAM timing waveform?
12. What is Read cycle and Write cycle?
13. What is Synchronous SRAMs?
14. What are the different types of Synchronous SRAMs?
15. What is DRAM?
16. Define Refresh operation in DRAM?
[
]
[
]
D)trc
30. clup de selection to output in tri state
A) Th2
]
D)trc
29. Clup select access time is ------------
A) Tl2
[
D)trc
D) Static RAM
[
]
D) ROM
[
]
D)twp
[
]
D) 5
[
]
D) none
[
]
D) Transistor
[
]
D) none
D) All the above
[
]
D) Data
[
]
D) None
17. Give the classification of semiconductor memories?
18. What are the different operating modes in Synchronous SRAMs?
19. What is Synchronous DRAMs?
20. What are the applications of ROM?
10 MARKS QUESTIONS
UNIT-V
1. a) Discuss how PROM,EPROM and EEPROM technologies differ from each other.
b) With the help of timing waveforms, explain read and write operation of SRAM.
2) a) Explain the necessity of two dimensional decoding mechanism in memories.
b) Draw the MOS transistor memory cell in ROM and explain its operation.
3) a)Draw the basic cell structure of dynamic RAM . What is the necessity of refresh cycle?
b) Explain the timing requirements of refresh operation.
4) Discuss in detail ROM access mechanism with the help of timing waveforms.
5) a) Explain the internal structure of 64X 1 DRAM. With the help of timing waveforms discuss DRAM access.
b) Explain the operation of synchronous SRAM with the help of its internal architecture.
6) a) Design an 8X4 diode ROM using 74X138 from the following data starting from the first
location.B,2,4,F,A,D,F,E.
b) Realize the logic function performed by 74X381 with ROM.
7) a) With the help of internal structure of a small SRAM and its timing diagram., describe read and write
operations performed in the SRAM.
b) Discuss the advantages and disadvantages of ROM based on combinational circuit design.
8) a) Discuss the concept along with the merits of two dimensional decoding for read only memory.
b) Briefly explain 2-4 decoders using an 8X4 ROM.
9) Explain briefly about: (a) RAM (b) SSRAM (c) DRAM (d) SDRAM.
10. Write Short notes on
a) What is Memory and what are different types?
b) What is Read mode?
c) What is Synchronous SRAMs?
d) Define Refresh operation in DRAM?
e) What are the applications of ROM?
***