Download example design

Design flow for an example of an expandable 4-bit binary counter in BCD
code using the FSM style
a) Entity to be designed:
Symbol and state diagram (you can also add a sketch of a timing diagram to
figure out and predict the waveforms as a function of time). There is also a
function table to explain the way signals works.
CE
Count enable input
CD
Clear direct input
Expandable
1-digit
BCD counter
TC10
(Terminal Count
output:)
CLK
4
Q(3..0) (This is the
output vector in BCD
code)
CE = 0
CE = 1
CD = 1 (this is the
asynchronous reset)
(TC10 = 0)
(Q = “0000”)
Num0
(TC10 = 0)
(Q = “0001”)
Num1
Num_i
Num9
(TC10 = 1**)
(Q = “1001”)
0≤i≤9
Num2
(TC10 = 0)
(Q = “0010”)
Fig. 1 The symbol and the state diagram for the counter (two different
state diagrams in this example)
Function table:
CE
0
1
Q+
Q
Q+1
Output in the future, which is after a clock rising edge
Disable counting, hold, do nothing
Up counting enabled: …, 0011, 0100, 0101, 0110, …
**conditions: TC10 = ‘1’ when CE = ‘1’ and Q = “1001”, else ‘0’
b) Proposed architecture using the typical finite state machine (FSM)
structure as the model [NEVER GO ON WITHOUT THIS STEP,
remember that figuring out which is going to be the circuit’s internal
architecture is the KEY point in this course].
Using concurrent assignments or a
signal-sensitive process
4
COMBINATIONAL
CIRCUIT
CC2
TC
4
Q[3..0]
CE
COMBINACIONAL
CIRCUIT
CC1
4
4
State Registre
(Usually D-FF)
future_state[3..0]
Using concurrent
assignments or a signalsensitive process
SIGNALS
CLK
CD
present_state[3..0]
4
Entity
State_registre (Clock and CD
sensitive process
Fig. 2 Adapting the general FSM diagram to the given problem
c) VHDL source file.
One thing is study VHDL from books and from Internet sites, which is
something we encourage you to do, and other thing completely different is to
write VHDL code that has to be easily analysed and assessed by your team
mates and the instructor in very short time. This is why all the class has to
follow a very tight coding conventions or styles. Therefore, to translate the
previous block diagram into a VHDL file, you have to follow always one of
these two alternatives:
- Generally, the CSD finite state machine style shown in
many examples from the subject, like this one from Unit 2.3.
- In the particular case of registers counters or frequency
dividers with a large number of states, the arithmetic library
has to be used, like in this example from Unit 2.5 (for
example future_state <= present_state + 1,
future_state <= D_in).
d) ModelSim Altera edition /Active HDL lattice Edition / Xilinx ISIM VHDLbased project to perform a functional simulation for verifying the system.
To input signal vectors use one of these alternatives:
 A TCL *.do macro to organise the input activity as prepared in
a)
 A VHDL test bech
e) Use the vendor software (Quartus-II / Xilinx ISE / Diamond, for CPLD or
FPGA devices, or ispLEVER Classic for Lattice CPLD or GAL devices)
for start a project for both :
 Check the RTL netlist and the State machine diagram (if any), and
 Synthesise the circuit
f) Pin assignment, fitting and assembling the final chip configuration files
g) Timed (or gate-level) simulation (or Proteus-ISIS for GAL devices) taking
into account all the delays written in the *.sdo / *sdf files to verify that the
final flattened synthesised circuit *.vdo works as predicted by the
specifications.
h) Device programming, laboratory prototyping, verification and
measurement of electrical parameters.