Download Template For Examination Papers

EO124
s
SCHOOL OF ENGINEERING
HONOURS DEGREE COURSE
LEVEL 1
SEMESTERS 1 and 2
2006/2007
DIGITAL ELECTRONICS
Examiner: C. S. Knight

Attempt ALL questions in Section A and
 Each question in Section A
THREE questions only in Section B

The total number of questions is 20

The time allowed is 3 hours
carries 5 marks

Each question in Section B
carries 25 marks

Figures in brackets indicate the
marks for parts of a question
Special Requirements:

General 74HCT series data

74HCT08 data

74HCT112 data
1/13
EO124
3/13
SECTION A
1) Part of a 2 Volt digital system contains a 74HCT08 chip. A data sheet for this device is
supplied.
For this chip, and for an assumed working temperature of 25 °C, determine the following:
a) The minimum voltage for a logic '1' output.
b) The worst-case noise margin.
c) Explain the term ‘propagation delay’ with reference to this integrated circuit (IC). What is
the maximum propagation delay for this IC operating under these conditions?
d) What is the major disadvantage of running this system from a 2 Volt supply as opposed to a
6 Volt supply?
(5)
2) Shown below is the circuit symbol for a particular type of logic gate:
A
X
B
For this gate:
a) State its function.
b) Write down its full truth table.
c) Write down the Boolean equation that represents its function.
d) If a clock signal is applied to input A and a logic 1 to input B, describe the output signal X in
relation to the applied clock signal on A.
(5)
EO124
4/13
3) a) Draw a circuit to represent the following Boolean equation:
P  X .Y .Z  Y .Z  X .Y
b) List the 74HCT series chips required to implement this design.
c) Explain how the number of chips could be reduced (without the use of De Morgan’s laws)
by making appropriate adjustments to the circuit.
(5)
4) Showing the methods:
a) Convert the binary number 1011 to decimal.
b) Convert the decimal number 147 to an 8-bit binary number.
c) Convert the hexadecimal number E3 to an 8-bit binary number.
d) Convert the binary number 01111010 to hexadecimal.
e) Convert the decimal number 38 to BCD (binary coded decimal).
(5)
EO124
5/13
5) a) A Karnaugh map of a Boolean function Y is given below:
Y
CD
AB
00
01
11
10
00
1
1
01
1
1
11
1
1
10
1
1
1
1
Find the minimised equation for Y.
b) State De Morgan’s laws. Hence convert the minimised equation for Y from part (a) into a
form that includes AND and NOT functions only (i.e.: no OR functions).
(5)
6) a) A simple synchronous counter comprises several flip-flops with some combinational logic as
feedback. The flip-flop has a set-up time of 8 nsec and a propagation delay (clock to output
Q) of 15 nsec. The combinational logic has a total propagation delay of 17 nsec. Calculate
the absolute maximum frequency at which this counter can operate.
b) Explain briefly the concepts of set-up time and hold time with respect to a flip-flop.
(5)
7) a) Explain briefly the function of the ‘library’ and ‘entity’ sections of a VHDL description of a
digital design.
b) List the three main types of VHDL architecture.
c) With respect to the simulation of a VHDL description, explain briefly the term ‘stimulator’
and list two types of stimulator.
(5)
EO124
6/13
8) An uncommented VHDL description of a simple circuit element is given below:
library ieee;
use ieee.std_logic_1164.all;
entity question8 is port
(ch: in std_logic;
I: in std_logic_vector(1 downto 0);
O: out std_logic);
end question8;
architecture module1 of question8 is
begin
process (ch,I)
begin
if ch='0' then O<=I(0);
else O<=I(1);
end if;
end process;
end module1;
Name the precise function of this circuit element and explain how it functions.
(5)
EO124
7/13
9) A diagram of a JK flip-flop taken from MultiSim is given below:
a) Draw the excitation table for this flip-flop.
b) The timing diagram below shows inputs applied to CLK, J, K, PR and CLR:
CLK
PR
CLR
J
K
For the time period shown, redraw the clock waveform and underneath it show the
waveform for Q. State any assumptions made.
(5)
10) a) Draw the circuit symbol for a simple tri-state inverting buffer with an active-low control
input.
b) Write down its truth table and explain its operation.
c) Describe an application where this type of device might be used.
(5)
EO124
8/13
11) The block diagram of a simple 3-bit comparator is shown below along with an incomplete
VHDL description.
aa
x
b
library ieee;
use ieee.std_logic_1164.all;
entity three_ip_comp is port
(a,b: in std_logic_vector(2 downto 0);
x: out std_logic);
end three_ip_comp;
architecture module1 of three_ip_comp is
begin
process (a,b)
begin
** Missing Code**
end process;
end module1;
The function is to be as follows: when the binary number on the 3-bit input ‘b’ is greater than
that on the 3-bit input ‘a’, the output 'x' will be a logic 0. For all other conditions, 'x' will be a
logic 1.
Complete the architecture section of the VHDL description such that the appropriate function is
achieved. It is only necessary for you to write down the missing code.
(5)
EO124
9/13
12) The simulation output of a VHDL design for a particular circuit is provided below. ‘clock0’ and
‘clear’ are binary inputs and ‘Q0’, ‘Q1’ and ‘Q2’ are binary outputs.
100
200
300
400
500
600
700
800
900
1000
1100
ns
clear
clock0
Q0
Q1
Q2
With respect to the waveform:
a) State and explain the precise function of the circuit.
b) Estimate the clock frequency used for this simulation.
QUESTION 13 STARTS ON THE NEXT PAGE.
(5)
EO124 10/13
13) The following is a VHDL description of a 4-bit mod-12 synchronous binary down counter with
a synchronous active-low clear input.
The code contains five errors. Identify these errors and show how they may be corrected.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is port (
bout
: inout unsigned(1 downto 0);
clk, clr : in std_logic );
end counter;
architecture bin_up of counter is
begin
count: process (clk, clr)
begin
if rising_edge(clk) then
if clr = '1' then
bout <= "000";
else
bout := bout – ‘001’;
end if;
if bout = ‘0000’ then
bout <= “1001”;
end if;
end;
end process count;
end bin_up;
(5)
EO124 11/13
14) A simple single-pole single-throw (SPST) switch is to be interfaced to one of the inputs of an
AND gate on a 74HCT08 logic chip (data sheet supplied) that is operating with a supply voltage
of 6 Volts. The input is to be ‘low’ when the switch is open and ‘high’ when the switch is
closed.
Draw a diagram of a suitable circuit arrangement and calculate the value of the resistor used. A
value of 0.1 A may be used for Iil.
(5)
15) The following Boolean equation is expressed in minterm form:
P  f (a, b, c) 
 (m , m , m , m , m , m
0
1
2
3
5
7)
Write down the full Boolean equation in sum-of-products form, draw a Karnaugh map of the
function and hence find the minimised Boolean equation.
(5)
EO124 12/13
SECTION B
16) Design a simple asynchronous mod-6 up counter using two 74HCT112 I.C.s (data given) and
appropriate combinational logic chips. List the chips used in your design and, with the aid of a
timing diagram, explain in detail how the circuit functions.
(25)
17) A synchronous sequence generator is required to produce the repeated waveforms as shown
below:
Clock
P(0)
P(1)
P(2)
a) Draw up a state diagram that describes this sequence.
(6)
b) From the state diagram in part (a), write a VHDL description for this sequence generator.
Ensure that the circuit is self-starting.
(19)
EO124 13/13
18) The block diagram of an 8-bit shift register is shown below:
clk
load/shift
bin
bout
Load/shift is a simple single binary input. bin is an 8-bit parallel input and bout is a parallel 8bit output. clk is the clock input.
The circuit function is as follows. On the application of a rising edge of the clock:
● when load/shift = ‘0’, then data applied to 'bin' is loaded into the register.
● when load/shift = ‘1’, then the data in the register is shifted right by one bit position.
a) Write a complete VHDL description for the circuit function.
(20)
b) What modifications would be required to implement a synchronous active-high clear input to
the shift register?
(5)
EO124 14/13
19) A synchronous self-starting modulo-5 binary down counter is required as part of a large digital
system.
a) Draw up a state diagram that describes this counter.
(6)
b) From the state diagram in part (a), develop a state table and hence derive the required
minimised flip-flop input equations for a design that uses flip-flops of your choice. State all
assumptions made.
(13)
c) Draw the circuit diagram for the design in part (b) assuming that the circuit will be
implemented using 74HCT series chips.
(6)
20) A switching network has three inputs and two outputs as shown in the block diagram given
below:
a
t1
b
t0
c
The output t1,t0 represents two bits of a binary number ‘t’. ‘t’ is to represent the number of
logic ‘0’s on the three inputs. For example, if abc = 101 then there is one ‘0’ so t = 01.
Draw up the truth table for this function and derive minimised equations for t1 and t0. Hence
produce a VHDL design for the circuit.
(25)