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Low-Power Design for
Embedded Processor
경종민
[email protected]
Low-Power Design for Embedded Processor
• Minimization of power consumption in portable and
battery-powered embedded systems has become an
important aspect of processor and system design.
• Opportunities for design tradeoffs emphasizing low
power are available across the entire spectrum of the
overall design process.
– From algorithm selection to silicon process technology
– Generally, the higher the level of abstraction, the greater the
opportunity for power savings.
Power Dissipation in CMOS Circuits
• Power dissipated in CMOS circuits
Ptotal  Pswitching  Pshortcircuit  Pstatic  Pleakage
– Pswitching and Pshortcircuit are present when a device is actively
changing state, while the component Pstatic and Pleakage are
present regardless of state changes
Power Dissipation in CMOS Circuits
• Pswitching: power required to charge or switch
capacitive load
Pswitching  Cef f  Vdd  f
2
– Reduction of supply voltage is an obvious candidate
technique for power reduction
• Performance reduced as Vdd is lowered due to reduced
saturation current to charge and discharge load capacitance
• Energy-delay product is minimized when Vdd is equal to
2*Vthreshold
Tdelay 
Cload  Vdd
Vdd  Vthreshold 
1.5
*
• However, as Vthreashold decreases, leakage current increases
exponentially
* A.Bellaur and M.I. Elmasry, Low Power Digital CMOS Design: Circuits and Systems, Kluwer 1996
Power Dissipation in CMOS Circuits
• Pshortcircuit: power consumed during output transitions of CMOS
gates as the input switches
Pshortcircuit  Imean  Vdd
– Imean represents the average current drawn during the input
transistion
– For a single gate, Imean becomes smaller with shorter input rise and
fall times, and with long output transition
– When a set of gates is considered, it is generally optimal to have
equal input and output transition times
• Pstatic: static power consumed by the deice
– not usually a factor in pure CMOS designs, since static current is
not drawn by a CMOS gate
– But certain circuit structures contribute to overall power
• E.g, sense amplifiers, voltage reference and constant current sources
Power Dissipation in CMOS Circuits
• Pleakage: leakage power consumed by the device
– Due to leakage currents from reversed biased PN junctions
associated with source and drain of MOS transistors, as well
as subthreshold conduction currents.
– The leakage components proportional to device area and
exponentially dependent on temperature
– The subthreshold leakage component is strongly dependent
on device threshold voltages, and becomes an important
factor as power supply voltage scaling is used to lower
power
– For systems with a high ratio of standby operation to active
operation, Pleakage may be the dominant factor
Design Techniques for Power Reduction
- Algorithmic
• Selection of an algorithm is generally based on details of an
underlying implementation
–
–
–
–
Cost of addition versus a logical operation
Cost of memory access
Locality of references
Presence of cache memory
• Loop unrolling is also of benefit, as it results in minimized loop
overhead
• Number representations offer another area for algorithmic power
tradeoffs.
– E.g., fixed-point or floating-point, signed-magnitude or two’s
complement
• Operator precision, or bit length
– Trade off between power and accuracy
Design Techniques for Power Reduction
- Architectural
• Instruction set design and exploitation of parallelism
and pipelining are important
• Architecture-driven voltage scaling
– Lowering supply voltage to reduce power consumption
– Apply parallelism and/or pipelining to maintain throughput
– Useful if enough parallelism exists but latency and area
overhead increases
• Low-power designs tend to avoid deep pipelining
– unless the amount of speculation is limited,
the overhead for speculation is low,
and accuracy of speculation is high
Design Techniques for Power Reduction
- Architectural
• Instruction set can have a large effect on power
dissipation as well as performance
– By careful selection of instruction semantics and
immediate/displacement widths, the size of code can be
reduced to 70%
• Utilizing cache memory
– Given that accessing the next level of the memory hierarchy
can result in 20x greater power consumption, the reduction
in miss rate due to doubling cache size is significant.
Design Techniques for Power Reduction
- Logic and Circuit Level
• Many techniques for power reduction are available at
the logic and circuit level
– Most focus on reducing the effective switched
capacitance(Ceff)
– Others focus on reduced signal swing, thus avoiding the
quadratic dependence on supply voltage
• Static and dynamic (clocked) logic families are both
utilized in CMOS designs.
– Depending on signal probabilities, one or the other may offer
reduced Ceff
Design Techniques for Power Reduction
- Logic and Circuit Level
• Logic restructuring for glitch elimination
– Static logic may suffer form hazards (or glitches) that result
in unnecessary power consumption
– Logic restructuring and path delay balancing may be used to
reduce glitch power
X
Y
Z
X
X'
Y'
Y
Z
Z
X
X
Y
X'
Hazard Generation
Z
Y'
Y
Y'
X'
X'
X Y  X  Y
Y'
Restructured logic to remove hazard
A. Raghunathan, et al., “Register transfer level power optimization with emphasis on glitch analysis
and reduction,” TCAD 1999
Design Techniques for Power Reduction
- Logic and Circuit Level
• Equivalent logic mappings with different power cost
– Transition probabilities of the logic being mapped are used in
conjunction with loading models of the library elements
– Select a mapping of the desired Boolean function onto a set
of gates which minimized power
p is the transition probability of a node in a dynamic logic = probability of the output being 0
V. Tiwari et al., “Technology mapping for low power,” DAC 1993
Design Techniques for Power Reduction
- Logic and Circuit Level
• Input and transistor reordering affect
– the amount of switched internal capacitance of the gate,
– the speed of the gate
– The static power dissipation
• Inputs signals with high probability of being off are placed
nearest the output node
When, PA(1) > PB(1) > PC(1)
W.-Z. Shen et al., “Transistor reordering rules for power reduction in CMOS gates,” ASP-DAC 1995
Design Techniques for Power Reduction
- Logic and Circuit Level
• Clock power reduction
– Clock power reduction is important in synchronous systems
• Can contribute to a large portion of the overall power budget
• 30%-40% of total system power is consumed by clock
generation and distribution
– Clock distribution optimization
– Clock gating
– Low-swing clocking techniques
Design Techniques for Power Reduction
- Logic and Circuit Level
• Clock distribution
– Efficient distribution and gating mechanisms are essential
– Example: two-level clock distribution network
Design Techniques for Power Reduction
- Logic and Circuit Level
• Gated clocking
– Commonly applied techniques
– Gating off of clock signals to registers, latches and clock
regenerators
• When there is no required activity to be performed
– May be applied at the function unit level or entire
subsystems
– Overhead associated with generation of the enable signal
must be considered
Design Techniques for Power Reduction
- Logic and Circuit Level
• Reduced swing clocking
– Reducing clock driver supply voltage by 50% and providing
specially designed flip-flops
• Theoretical power saving of 75% and reported savings of 63%
• Increases flip-flop delay by > 2x
• Differential clock signaling
– Allows the clock swing to be reduced well below 50% of Vdd
• Typically consumes static power
• With 0.2xVdd swing, theoretical saving in the clock network is
60%
H. Kojima et al. “Half-swing clocking scheme for 75% power saving in clocking circuitry,” JSSC 1995
J.-C. Kim, “A high-speed 50% power saving half-swing clocking scheme for flip-flop with
complementary gate and source drive,” ICVC 1999
Design Techniques for Power Reduction
- Logic and Circuit Level
• Precomputation structure
– Minimizes switching activity by selectively precomputing the
output values of a logic circuit before they are required
– And then using the computed values to minimize switching
activity by disabling inputs
– Reported power saving is 11%-66%
Subset of terms which makes F = 1
Subset of terms which makes F = 0
Design Techniques for Power Reduction
- Device Technology
• Threshold voltage selection
– Plays an important role in the tradeoff between performance and
leakage power
• Silicon on Insulator(SOI)
– Attractive due to lowered parasitic capacitance and reduced body
effect
• Dual device threshold technologies
– Also an approach to lowering power consumption
• High-threshold devices for non-critical delay paths
• Low-threshold devices for speed-critical paths
– Minimizing standby power consumption
• Well biasing
– Raises the threshold of all devices
– Reduces standby power
Standby Power Reduction
Standby Power Modes
Hitachi SH4 Substrate Bias Technique
Hitachi SH4 Substrate Bias Technique
Intel XScale Leakage Control
Intel XScale Power Modes
Super Cut-off CMOS (SCCMOS)
Delay Comparison (Inverter & NAND)
Structural and Dynamic Techniques
Voltage Scaling
Dual-VTH Concept