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Power distribution for SLHC trackers:
challenges and solutions
Marc Weber, RAL
TWEPP, Prague 2007
Independent powering fails at SLHC
Solving the PD problem is challenging and urgent
Choices will shape overall tracker design
Need strong collaboration to pull this off
1
Why power systems matter ?

LHC trackers are power hungry with ~O(10-100 kW)

Power supplies and cables are expensive

Power line is easiest way to get noise into detector or to kill it

Power cables are massive and bulky
Trend to systems with more channels, larger area and more
power is driven by physics (and technology) and will continue
2
From LHC to SLHC
Channels in millions
Strips A
Strips B
Pixel A
180
160
140
120
100
80
60
40
20
0
by factor 2-10 depending on radius,
η and technology
SSPPCB
2008
2016
year
Strips A
Technology  0.25 m processes
disappear
Strips B
5
4
-reduced ASIC size reduces mass
-reduced voltage saves power
3
Volts
Physics  more channels
 Hybrid
2
1
0
2008
2016
year
Strips A
Physicists/technology  little current
reduction
Pixel A
Power/channel [uW]
10000
-increased subthreshold leakage
-enhanced functionality
1000
100
10
2008
year
2016
Total current and power go up!
3
Why independent powering fails at SLHC ?
Current per chip ~ constant, but many more channels
1. Don’t get 5 or 10 times more cables in
2. Power efficiency is too low (50% ATLAS SCT  ~15% SLHC)
3. Cable material budget: 0.2% of R.L. per layer (barrel normal
incidence)  1% or 2% SLHC
4. Packaging constraints
Each reason by itself is
probably sufficient for a
No-No
4
Elements of power systems
Off-detector power supply
Power distribution
scheme: IP; SP; PP
+ cables
On-detector
power supplies:
Monitor + control
regulators; converters;
transformers
IP: independent powering;
SP: Serial powering;
system
PP: parallel powering
On-detector supplies and the distribution scheme are most urgent,
but we need all elements eventually
5
Power distribution specs
It would be nice to define a spec list and get back the solution in two
years, but this is not how it works

Power distribution closely intertwined with ASIC, hybrid and
module design (also with cooling system and overall tracker layout)

Results of power distribution R&D will influence the above
strongly  specs are somewhat fluid

Experience with local high power regulation in HEP community
is limited  have to learn what can be done
Let’s look at ATLAS SLHC strips as representative example
6
ATLAS SemiConductorTracker barrel
1 hybrid per double-sided module; 12 chips; ~5 W; ~1.5 A
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Short strips at SLHC
2.5 cm short strips on 10 cm x 10 cm wafer  channel density
increase over SCT by factor ~5
Could have 1 or 2 hybrids per single-sided module with 20 or 40 chips
per hybrid!
ROIC
Local power
supply
Typical power/current estimates:
~5 W at 4 A for 20 chips
4 columns of
strips per sensor
Limit current at all costs! Think twice
about fancy new features and ultimate
performance  powering R&D
8
Constraints
Radiation:
1016-1014 n/cm2  custom ASICSs  Hybrid
Magnetic field:
2-4 T  standard ferrite coils saturate
SSPPCB
Reliability: no access during lifetime of experiments; watch failure
modes that cost several modules (serial and parallel powering)
“EMI”: signals are small and sensors can be very sensitive to “pickup” (certainly strips); AC lines; switching action; IR drops, etc.
need to be controlled carefully
Size and mass:
miniaturization is mandatory
Materials: limits for materials that are magnetic or can be activated
Tracking environment is extremely challenging
9
Alternative power distribution schemes
So far we have identified the following schemes

Serial powering

DC-DC conversion with air-coil inductors

DC-DC conversion with switched capacitors
In practice, the DC-DC schemes involve parallel powering
We will learn about another very interesting alternative including
piezo transformers in the talk of Masatoshi Imori
10
SP history
Idea is old, but was only seriously considered a couple of years ago
Pioneering work was done by Bonn group for pixels
RAL picked it up 2 years ago for strips
SP approach is somewhat unorthodox, which makes it interesting.
“Only a physicist can be crazy enough to try this!” Bob Ely on SP
On the other hand, all approaches to the power distribution problem go
against conventional wisdom and practice…
11
How does SP work?
Elements
1. Current source (external power supply)
2. Shunt regulator and shunt transistor (digital power)
3. AC or opto-coupling of signals
Linear regulators provide analog power. This is independent
of SP and saves a factor 2 in cables/connections
Giulio Villani will give a proper introduction to SP and
present latest results. I will limit my discussion to three
fundamental implementation choices, which we will explore over
the next year.
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SP architecture choices
a) External shunt regulator + external power transistor
Voltage chain
5 V
ROIC ROIC ROIC ROIC
Module 1
Constant
current
source
2.5 V
Module n
0V
External commercial SR, used for RAL silicon strip studies
With custom electronics could be part of one or two chips
This is good engineering, but implies a high-current device; limited
expertise in HEP IC community; limits hybrid current
13
SP architecture choices
b) Shunt regulator + transistor in each ROIC
Integrated (custom) SR and transistor used for Bonn pixel results
Many power supplies in parallel;
Difficulty is matching and switch-on behaviour of shunt transistor
14
SP architecture choices
c) External shunt regulator + integrated parallel power
transistors
New attractive idea. Addresses high-current limitation.
Need to understand properties of distributed feed-back
Which architecture works best will depend on application. We hope to
explore all three
15
SP features and status
SP “recycles” current from module to module:  reduced thermal
losses; increased power efficiency
Constant current eliminates IR drops  quiet systems
AC-coupling of data and control signals is a minor nuisance if
engineered properly
Noise performance is looking very good, but we need another ½ year
or so too understand these systems in depth
Reliability is an important theme and so is high current operation
16
DC-DC conversion
There are three main activities at this stage:
Custom buck converter with air coil inductor (see talk by
Stefano Michelis and Federico Faccio)
Exploration of commercial air coil buck converters (see talk
by Satish Dhawan)
DC-DC conversion with switched capacitors (Bob Ely,
Maurice Garcia-Sciveres, Peter Denes)
I will first show a few slides by Maurice on the switched capacitor
conversion, which is not covered elsewhere at TWEPP
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DC-DC conversion with switched capacitors
Example: divide by 4 stack: 4 capacitors – 10 switches
Phase 1 - Charge
2
1
1
VPS
Load
2
2
1
2
Phase 2 - Discharge
2
1
2
VPS
2
Load
1
Load
Charge and discharge different arrangements of capacitors to convert
“high” input voltage to low module voltage
Challenge is design of switching chip and to supply sufficient current
18
DC-DC conversion with switched capacitors
Example: divide by 4 stack: 4 capacitors – 10 switches
Phase 1 - Charge
2
1
1
VPS
Load
2
2
1
Phase 2 - Discharge
2
2
VPS
1
Load
2
2
1
Load
Charge and discharge different arrangements of capacitors to convert
“high” input voltage to low module voltage
Challenge is design of switching chip and to supply sufficient current
19
Why switched capacitors?
• Commercial DC-DC down-converters for power
applications are all inductive.
– Switched capacitors used to step-up voltage at low power to
drive displays, etc.
• Why then study switched capacitors for power?
– Cannot use ferrites in magnetic field => performance penalty
for magnetic converters
– With magnetic converters fringe AC magnetic fields may
produce pickup in detectors (must study case-by-case)
– Ceramic capacitor miniaturization makes great advances
year after year (but air-core inductors cannot be improved).
– Over-voltage safety considerations
20
LBNL prototype switching IC
P. Denes, R. Ely, M. Garcia-Sciveres
•
•
•
•
•
Received May 2007
50 V (source to drain) 0.35 m HV CMOS process
10 power switches in 4.3 x 4.9 mm footprint
All capacitors external, all clocks external
Chip re-submitted Aug. 14, 2007 with bias circuit fix AND external
override
Does not work outside
shown voltage range due to
problems with bias circuit
Low power efficiency is due to
large current consumption in
bad bias circuit. Expect ~75%
after fix.
21
Plans for next iteration
• Expected delivery date Nov. 5
• Concentrate on building “plug and play” prototypes that can be used
to power existing and new detector assemblies.
• Target format:
2cm
1cm
0.5A device
3cm
1cm
1A device
• Inputs: Power (I_out/4), +4V (~20mA), Clock (optional).
• Miniaturization challenging because several external components
needed.
• In eventual production size could be further reduced (ultimate goal is
1 cm2/Amp of output) by absorbing more functionality into ASIC.
22
DC-DC features and status
Approach is to minimize current during distribution:
low I, high V + local conversion  reduced thermal losses; increased
power efficiency
DC-DC scheme can be implemented with independent or parallel
powering. Parallel powering with local converters on each module is
most natural
Concept is more conventional than SP. Big challenge is tracking
environment
Most critical and urgent in my view are:
switching high currents without injecting noise into sensors;
development of custom radiation hard “high voltage” ASIC
Understand system properties: failure modes and protection, slowcontrol; cable budget; real estate
23
Let’s work out a powering example
here VROIC = 2.5 V; IH = 2.4 A; 20 hybrids; DC-DC gain = 20
SP: n=20; IH = IPS = 2.4 A; VPS = nVROIC = 50 V
Features: saves factor ~8 in power cables/length over ATLAS SCT
1
2
3
4
5
6
n-1
n
DC-DC PP: n=20; g = 20; IPS = n/g IH = 2.4 A; VPS = gVROIC = 50 V
Features: saves factor ~8 in power cables as SP, watch IR drops  Rcable ~ 0.1-1 Ω
DC-DC IP: n=1; g = 20; IPS = IH/g = 0.12 A; VPS = gVROIC = 50 V
Features: 2x more cables than SCT  problematic for strips
24
Power efficiency
Consider n modules with module current and voltages I and V, off-detector cable
resistance R, DC-DC gain g, define x= IR/V



power consumed by n modules is always: n I V
power wasted in the cable depends on powering scheme
Low V is bad, large R and I are bad
here we consider cable
losses only
Ism
Vdrop
Vsm
Pcab
Efficiency:
Psm/Ptotal
IP
n I
IR
V
n I2R
1/[1 + x]
PP
n I
n IR
V
n2 I 2 R
1/[1 + nx]
SP
I
IR
nV
I2 R
1/[1 + x/n]
DCDC
(n/g) I (n/g) I gV
R
(n/g)2
I2 R
1/[1 + xn/g2]
Just plug in your numbers
and then consider regulator
inefficiency
All new schemes will be
much better than IP
25
Power efficiency for SP at LHC and SLHC
Illustration of various cases:
SCT  4V, 1.5 A, R= 4.5   x=1.14; IP
SLHC  2.5V, 2.4 A, R= 4.5   x=4.3; SP (only cable losses)
SLHC  1.5V, 4 A, R= 4.5   x=12; SP (only cable losses)
same but including SR power and LR power (extrapolated from ATLAS SCT measurements)
Keep hybrid current
low!
1.000
0.900
SR inefficiency ~7% for
0.800
Efficiency
0.700
SLHC x= 4.3
0.600
10% digital current variation
SLHC x= 12
SCT x= 1.14
0.500
SP
0.400
SP+LR
LR for analog has
similar losses
0.300
0.200
0.100
0.000
0
5
10
15
20
number of modules
25
30
SR inefficiency is
reduced for 0.13 m
CMOS
26
System design: slow control
For IP, we have external information on module voltage and current
consumption
This is not true for SP or PP DC-DC systems
It is desirable to implement a slow-control system on SLHC silicon
tracker modules  get rid of sense wires; need to control
redundancy and protection features of the new powering circuitry
remotely
Should investigate and specify slow-control logic and bus on the
hybrid
27
Features of IP and alternative schemes
IP
SP
DC-DC
Comment
10-20%
60-80%
60-80%
Varies with I, n (SP);
gain (DC-DC)
0%
~10%
<20%
This is without linear
regulator for analog
number of
power cables
4 per hybrid
Reduction by factor 2n
Reduction by factor 2n
Voltage control
over ind. hybrids
Yes
On/Off; fineadjustment
Stand-by mode:
2.5V/1.5V -> 0.7 V;
Yes
On/Off; limited fineadjustment
New schemes have
regulators; no fine
adjustment needed
(sensing
current
through power device)
Yes
Some power penalty
for DC-DC
(need
sense wires)
Yes
Yes
Not strictly needed,
since regulators
Yes
No, voltage chain
No
Separate set
of cables for
each hybrid
Local
over-current
protection; redundant
regulators
Don’t know yet
Power efficiency
Local regulator
inefficiency
Yes
Hybrid current
info
Hybrid voltage
info
Floating hybrid
power supplies
Protection
features
Yes
Limited fine-adjustment
Yes
n = number
hybrids
of
Protect against open
(SP) and short (DCDC)
Let’s preserve the good features of IP  have voltage control, current
monitoring, and protection features
28
R&D timeline
Aim for implementation of advanced SP and DC-DC conversion PP
systems in a realistic (supermodule prototypes in ~ 3 years
Can distinguish three main phases
1.
Generic studies to identify basic features and challenges 
electrical performance, grounding and shielding, power
efficiency, redundancy…
2.
Develop radiation-hard custom electronics (Shunt regulators;
DC-DC switching chip);
build and test systems with large number of modules
3.
Implementation of power distribution schemes on advanced
supermodule prototypes  crucial to establish supermodule
electrical performance before production
29
Where are we now ?
Disclaimer: this is just my view and in ½ year it might look very differently…
Generic Studies
SP Pixel
SP Strips
DC-DC capacitors
DC-DC inductors
Custom IC
First ICs in ~6 m
Multi-mod. Systems
Implementation
6 modules in ~1 m
Commercial ICs and
custom switches
Piezo transformer
SP generic studies are advanced and look promising for both strips and pixels. Strips
will get custom first generation of custom electronics in spring 2008
DC-DC conversion with air coil inductor: first generation of boards with
commercial components are available. Test station to characterize performance
is being build up. Commercial ICs are being evaluated.
DC-DC conversion with switched capacitors: fully functional chip expected
November 2007. This will also be the start of generic studies
Implementation phase will not be reached before 2-3 years from now
30
Communication/collaboration
Collaboration across technologies, experiments and between detector builders and
electronic engineers

Use collective expertise and increase manpower (LHC is first priority
for many of us!)

Develop PD specifications together with detector system
designers (find right balance between generic and detector-specific R&D)

Get the physicists to test your devices in a system

Share the costs (prototyping with silicon modules is expensive
and so are industrial partners)
Without collaboration, we won’t have resources to develop all
technology to maturity
31
Ideas for discussion

Have experiment internal organizations and power distribution
activity within EU PF7 framework (5 partners). The latter is
expected to be focal point of larger collaboration

Focus will be on LHC tracker upgrades, but could be broader

Should maintain the breadth of the program for at least another 2
years or so.

Frequency and type of workshops:
-need to get down to technical details
-avoid duplication of meetings/structure

At some stage (< 1 year) we need a review structure, clear
definition of commitments and possible a common fund
-which structure/review body
-when start setting this up?
32
Outlook
Without solving the PD problem, SLHC trackers willnot
Hybridwork
SSPPCB
Challenge is a big and pressing. We need to be focussed and
collaborate efficiently
We have the opportunity to get rid of the service congestion and
build much better detectors. Let’s do it!
Trend to large detector area, increased channel density and high
resolution continues at ILC, synchrotron radiation facilities and in
space science instrumentation
 our solutions will find wide application
33
Appendix
34
Transistor curves before and after 10MRad
This seems real.
Need to irradiate
more chips
35
At peak load
Simulation results: effect of clock
frequency
Load-independent
charge lost in switch
parasitics
Load-dependent.
Dominated by
switch resistance
36